[PATCH v3 0/3] OMAP: DSS2: Fix for DISPC core functional clock divider

[Tomi Valkeinen]

On Thu, 2011-03-03 at 09:27 -0600, Murthy, Raghuveer wrote:
> OMAP4 has 2 LCD channels and corresponding DISPC_DIVISOR1 and DISPC_DIVISOR2
> registers to configure the pixel clock frequency, for the respective LCD
> displays.
> 
> There is also DISPC_DIVISOR register, which by default has the ENABLE bit
> set to zero, for backward compatibility mode. Hence the logical clock divider of
> DISPC_DIVISOR1.LCD, gets used for core func clk configuration. The default value
> of DISPC_DIVISOR1.LCD is 4.
> 
> If only the secondary LCD is enabled, at high pixel resolutions the core clk 
> lags behind the pixel clock, causing stair-step effect (diagonal lines with
> tearing) on the display.
> 
> Hence DISPC_DIVISOR.ENABLE is set to 1, and the core functional clock is set 
> independently and exclusively in DISPC_DIVISOR.LCD.
> 
> - Added the above as dss_features

Thanks, applied.

 Tomi