Store buffer and l2x0_cache_sync

Colin Cross ccross at
Tue Mar 1 20:25:34 EST 2011

l2x0_cache_sync on a PL310 has no wait after the writel_relaxed to the
L2X0_CACHE_SYNC register, because PL310 cache operations are atomic.
Doesn't the cpu store buffer still need to be flushed after the
register write, either with a dsb or a dummy read?

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