No subject
Mon Jun 27 16:47:34 EDT 2011
mx28 are the same.
Then it might be better to name the file regs-usbphy-mxs.h instead of
regs-usbphy-mx28.h.
Koen
On Mon, Jul 25, 2011 at 9:01 AM, Tony Lin <tony.lin at freescale.com> wrote:
> add usb phy register definitions and functions
> usb host driver will use these callback functions
> to initialize usb phy and change working mode
>
> Signed-off-by: Tony Lin <tony.lin at freescale.com>
> ---
> =C2=A0arch/arm/mach-mxs/Kconfig =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0=
| =C2=A0 =C2=A01 +
> =C2=A0arch/arm/mach-mxs/Makefile =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 | =C2=
=A0 =C2=A01 +
> =C2=A0arch/arm/mach-mxs/mxs_usb.c =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0| =C2=
=A0286 ++++++++++++++++++++++++++++++++++
> =C2=A0arch/arm/mach-mxs/regs-usbphy-mx28.h | =C2=A0240 ++++++++++++++++++=
++++++++++
> =C2=A04 files changed, 528 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig
> index 4cd0231..1c4264f 100644
> --- a/arch/arm/mach-mxs/Kconfig
> +++ b/arch/arm/mach-mxs/Kconfig
> @@ -49,6 +49,7 @@ config MACH_MX28EVK
> =C2=A0 =C2=A0 =C2=A0 =C2=A0select MXS_HAVE_PLATFORM_MXS_MMC
> =C2=A0 =C2=A0 =C2=A0 =C2=A0select MXS_HAVE_PLATFORM_MXSFB
> =C2=A0 =C2=A0 =C2=A0 =C2=A0select MXS_OCOTP
> + =C2=A0 =C2=A0 =C2=A0 select USB_ARCH_HAS_EHCI
> =C2=A0 =C2=A0 =C2=A0 =C2=A0help
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Include support for MX28EVK platform. T=
his includes specific
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0configurations for the board and its pe=
ripherals.
> diff --git a/arch/arm/mach-mxs/Makefile b/arch/arm/mach-mxs/Makefile
> index 6c38262..726c49f 100644
> --- a/arch/arm/mach-mxs/Makefile
> +++ b/arch/arm/mach-mxs/Makefile
> @@ -12,5 +12,6 @@ obj-$(CONFIG_MACH_MX23EVK) +=3D mach-mx23evk.o
> =C2=A0obj-$(CONFIG_MACH_MX28EVK) +=3D mach-mx28evk.o
> =C2=A0obj-$(CONFIG_MODULE_TX28) +=3D module-tx28.o
> =C2=A0obj-$(CONFIG_MACH_TX28) =C2=A0 =C2=A0+=3D mach-tx28.o
> +obj-$(CONFIG_USB_EHCI_MXC) =C2=A0 +=3D mxs_usb.o
>
> =C2=A0obj-y +=3D devices/
> diff --git a/arch/arm/mach-mxs/mxs_usb.c b/arch/arm/mach-mxs/mxs_usb.c
> new file mode 100644
> index 0000000..01753ea
> --- /dev/null
> +++ b/arch/arm/mach-mxs/mxs_usb.c
> @@ -0,0 +1,286 @@
> +/*
> + * Copyright (C) 2009-2011 Freescale Semiconductor, Inc. All Rights Rese=
rved.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. =C2=A0See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License alo=
ng
> + * with this program; if not, write to the Free Software Foundation, Inc=
.,
> + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
> + */
> +
> +#include <linux/kernel.h>
> +#include <linux/types.h>
> +#include <linux/clk.h>
> +#include <linux/delay.h>
> +#include <linux/platform_device.h>
> +#include <linux/io.h>
> +#include <linux/err.h>
> +#include <linux/fsl_devices.h>
> +#include <linux/gpio.h>
> +#include <asm/mach-types.h>
> +#include <asm/mach/arch.h>
> +#include <mach/irqs.h>
> +#include <mach/mx28.h>
> +#include "regs-usbphy-mx28.h"
> +
> +/* EHCI registers: */
> +#define UOG_USBCMD =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (0x140) /* =
USB command register */
> +#define UOG_USBSTS =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (0x144) /* =
USB status register */
> +#define UOG_PORTSC1 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(0x184) /* =
port status and control */
> +/* x_PORTSCx */
> +#define PORTSC_PTS_MASK =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0=
=C2=A0(3 << 30) /* parallel xcvr mask */
> +#define PORTSC_PTS_UTMI =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0=
=C2=A0(0 << 30) /* UTMI/UTMI+ */
> +#define PORTSC_PTW =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (1 << 28) /=
* UTMI width */
> +/* USBCMD */
> +#define UCMD_RUN_STOP =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (1 << 0) /* con=
troller run/stop */
> +#define UCMD_RESET =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (1 << 1) /*=
controller reset */
> +
> +#define HOSTPHY_CONNECT_STATE =C2=A0(1 << 3)
> +#define STS_PCD =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =
=C2=A0 =C2=A0 =C2=A0 =C2=A0(1 << 2) /* port change detect */
> +
> +struct mxs_usb_private_date {
> + =C2=A0 =C2=A0 =C2=A0 struct clk *usb_clk, *usb_phy_clk;
> + =C2=A0 =C2=A0 =C2=A0 int internal_phy_clk_already_on;
> + =C2=A0 =C2=A0 =C2=A0 void __iomem *phy_regs; =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 /* usb phy register base */
> + =C2=A0 =C2=A0 =C2=A0 void __iomem *ctrl_regs; =C2=A0 =C2=A0 =C2=A0 =C2=
=A0/* usb controller register base */
> +};
> +
> +static inline int fsl_platform_get_usb_connect_status
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =
=C2=A0 (struct mxs_usb_private_date *ppriv)
> +{
> + =C2=A0 =C2=A0 =C2=A0 u32 status;
> +
> + =C2=A0 =C2=A0 =C2=A0 status =3D __raw_readl(ppriv->phy_regs + HW_USBPHY=
_STATUS);
> +
> + =C2=A0 =C2=A0 =C2=A0 return ((status & HOSTPHY_CONNECT_STATE) =3D=3D 0)=
;
> +}
> +
> +/* enable/disable high-speed disconnect detector of phy ctrl */
> +static inline void fsl_platform_disconnect_detect
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =
=C2=A0 (struct mxs_usb_private_date *ppriv, int enable)
> +{
> + =C2=A0 =C2=A0 =C2=A0 if (enable) {
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 __raw_writel(BM_USBPHY=
_CTRL_ENHOSTDISCONDETECT,
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 ppriv->phy_regs + HW_U=
SBPHY_CTRL_SET);
> + =C2=A0 =C2=A0 =C2=A0 } else {
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 __raw_writel(BM_USBPHY=
_CTRL_ENHOSTDISCONDETECT,
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 ppriv->phy_regs + HW_U=
SBPHY_CTRL_CLR);
> + =C2=A0 =C2=A0 =C2=A0 }
> +}
> +
> +static void fsl_plt_usbh_irq_handler(struct mxc_usbh_platform_data *pdat=
a)
> +{
> + =C2=A0 =C2=A0 =C2=A0 u32 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0 =C2=A0 =C2=A0 status;
> + =C2=A0 =C2=A0 =C2=A0 struct mxs_usb_private_date *ppriv =3D pdata->ppri=
v;
> +
> + =C2=A0 =C2=A0 =C2=A0 status =3D __raw_readl(ppriv->ctrl_regs + UOG_USBS=
TS);
> +
> + =C2=A0 =C2=A0 =C2=A0 if (status & STS_PCD)
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 fsl_platform_disconnec=
t_detect(ppriv,
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =
=C2=A0 fsl_platform_get_usb_connect_status(ppriv));
> +}
> +
> +static int usb_phy_enable(struct mxc_usbh_platform_data *pdata)
> +{
> + =C2=A0 =C2=A0 =C2=A0 u32 tmp;
> + =C2=A0 =C2=A0 =C2=A0 u32 i =3D 0;
> + =C2=A0 =C2=A0 =C2=A0 struct mxs_usb_private_date *ppriv =3D pdata->ppri=
v;
> + =C2=A0 =C2=A0 =C2=A0 void __iomem *usbcmd, *phy_ctrl, *portsc;
> +
> + =C2=A0 =C2=A0 =C2=A0 /* Reset USB IP */
> + =C2=A0 =C2=A0 =C2=A0 /* Set run stop bit */
> + =C2=A0 =C2=A0 =C2=A0 /* Send reset command */
> + =C2=A0 =C2=A0 =C2=A0 usbcmd =3D ppriv->ctrl_regs + UOG_USBCMD;
> + =C2=A0 =C2=A0 =C2=A0 tmp =3D __raw_readl(usbcmd); /* usb command */
> + =C2=A0 =C2=A0 =C2=A0 tmp &=3D ~UCMD_RUN_STOP;
> + =C2=A0 =C2=A0 =C2=A0 __raw_writel(tmp, usbcmd);
> + =C2=A0 =C2=A0 =C2=A0 while (__raw_readl(usbcmd) & UCMD_RUN_STOP) {
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 i++;
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 if (i =3D=3D 1000)
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =
=C2=A0 break;
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 mdelay(1);
> + =C2=A0 =C2=A0 =C2=A0 }
> + =C2=A0 =C2=A0 =C2=A0 tmp |=3D UCMD_RESET;
> + =C2=A0 =C2=A0 =C2=A0 __raw_writel(tmp, usbcmd);
> + =C2=A0 =C2=A0 =C2=A0 i =3D 0;
> + =C2=A0 =C2=A0 =C2=A0 while (__raw_readl(usbcmd) & UCMD_RESET) {
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 i++;
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 if (i =3D=3D 1000)
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =
=C2=A0 break;
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 mdelay(1);
> + =C2=A0 =C2=A0 =C2=A0 }
> + =C2=A0 =C2=A0 =C2=A0 mdelay(10);
> +
> + =C2=A0 =C2=A0 =C2=A0 /* Reset USBPHY module, set soft reset bit */
> + =C2=A0 =C2=A0 =C2=A0 phy_ctrl =3D ppriv->phy_regs + HW_USBPHY_CTRL;
> + =C2=A0 =C2=A0 =C2=A0 tmp =3D __raw_readl(phy_ctrl);
> + =C2=A0 =C2=A0 =C2=A0 tmp |=3D BM_USBPHY_CTRL_SFTRST;
> + =C2=A0 =C2=A0 =C2=A0 __raw_writel(tmp, phy_ctrl);
> + =C2=A0 =C2=A0 =C2=A0 udelay(10);
> +
> + =C2=A0 =C2=A0 =C2=A0 /* clear CLKGATE and SFTRST bits to be out of rese=
t mode*/
> + =C2=A0 =C2=A0 =C2=A0 tmp =3D __raw_readl(phy_ctrl);
> + =C2=A0 =C2=A0 =C2=A0 tmp &=3D ~(BM_USBPHY_CTRL_CLKGATE | BM_USBPHY_CTRL=
_SFTRST);
> + =C2=A0 =C2=A0 =C2=A0 __raw_writel(tmp, phy_ctrl);
> + =C2=A0 =C2=A0 =C2=A0 udelay(10);
> +
> + =C2=A0 =C2=A0 =C2=A0 /* set UTMI xcvr */
> + =C2=A0 =C2=A0 =C2=A0 /* Workaround an IC issue for ehci driver:
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0* when turn off root hub port power, EHCI se=
t
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0* PORTSC reserved bits to be 0, but PTW with=
0
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0* means 8 bits tranceiver width, here change
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0* it back to be 16 bits and do PHY diable an=
d
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0* then enable.
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0*/
> + =C2=A0 =C2=A0 =C2=A0 portsc =3D ppriv->ctrl_regs + UOG_PORTSC1;
> + =C2=A0 =C2=A0 =C2=A0 tmp =3D __raw_readl(portsc);
> + =C2=A0 =C2=A0 =C2=A0 tmp &=3D =C2=A0~PORTSC_PTS_MASK;
> + =C2=A0 =C2=A0 =C2=A0 tmp |=3D (PORTSC_PTS_UTMI | PORTSC_PTW);
> + =C2=A0 =C2=A0 =C2=A0 __raw_writel(tmp, portsc);
> +
> + =C2=A0 =C2=A0 =C2=A0 /* Power up the PHY */
> + =C2=A0 =C2=A0 =C2=A0 __raw_writel(0, ppriv->phy_regs + HW_USBPHY_PWD);
> + =C2=A0 =C2=A0 =C2=A0 return 0;
> +}
> +
> +static int fsl_usbh_init(struct platform_device *pdev)
> +{
> + =C2=A0 =C2=A0 =C2=A0 struct mxc_usbh_platform_data *pdata =3D pdev->dev=
.platform_data;
> + =C2=A0 =C2=A0 =C2=A0 struct mxs_usb_private_date *ppriv =3D pdata->ppri=
v;
> + =C2=A0 =C2=A0 =C2=A0 u32 tmp;
> +
> + =C2=A0 =C2=A0 =C2=A0 usb_phy_enable(pdata);
> + =C2=A0 =C2=A0 =C2=A0 /* enable FS/LS device */
> + =C2=A0 =C2=A0 =C2=A0 tmp =3D __raw_readl(ppriv->phy_regs + HW_USBPHY_CT=
RL);
> + =C2=A0 =C2=A0 =C2=A0 tmp |=3D (BM_USBPHY_CTRL_ENUTMILEVEL2 | BM_USBPHY_=
CTRL_ENUTMILEVEL3);
> + =C2=A0 =C2=A0 =C2=A0 __raw_writel(tmp, ppriv->phy_regs + HW_USBPHY_CTRL=
);
> +
> + =C2=A0 =C2=A0 =C2=A0 return 0;
> +}
> +
> +static void phy_clock_gate(struct mxs_usb_private_date *ppriv, bool on)
> +{
> + =C2=A0 =C2=A0 =C2=A0 u32 tmp;
> +
> + =C2=A0 =C2=A0 =C2=A0 if (on) {
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 ppriv->internal_phy_cl=
k_already_on +=3D 1;
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 if (ppriv->internal_ph=
y_clk_already_on =3D=3D 1) {
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =
=C2=A0 tmp =3D BM_USBPHY_CTRL_SFTRST | BM_USBPHY_CTRL_CLKGATE;
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =
=C2=A0 __raw_writel(tmp, ppriv->phy_regs + HW_USBPHY_CTRL_CLR);
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 }
> + =C2=A0 =C2=A0 =C2=A0 } else {
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 ppriv->internal_phy_cl=
k_already_on -=3D 1;
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 if (ppriv->internal_ph=
y_clk_already_on =3D=3D 0) {
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =
=C2=A0 tmp =3D BM_USBPHY_CTRL_CLKGATE;
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =
=C2=A0 __raw_writel(tmp, ppriv->phy_regs + HW_USBPHY_CTRL_SET);
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 }
> + =C2=A0 =C2=A0 =C2=A0 }
> + =C2=A0 =C2=A0 =C2=A0 if (WARN_ON(ppriv->internal_phy_clk_already_on < 0=
))
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 printk(KERN_ERR "pleas=
e check phy clock ON/OFF sequence\n");
> +}
> +static int fsl_usb_host_init(struct platform_device *pdev)
> +{
> + =C2=A0 =C2=A0 =C2=A0 struct mxc_usbh_platform_data *pdata =3D pdev->dev=
.platform_data;
> + =C2=A0 =C2=A0 =C2=A0 struct mxs_usb_private_date *ppriv =3D pdata->ppri=
v;
> +
> + =C2=A0 =C2=A0 =C2=A0 ppriv->phy_regs =3D ioremap(MX28_USBPHY1_BASE_ADDR=
, SZ_8K);
> + =C2=A0 =C2=A0 =C2=A0 if (ppriv->phy_regs =3D=3D NULL)
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 return -ENOMEM;
> +
> + =C2=A0 =C2=A0 =C2=A0 ppriv->ctrl_regs =3D ioremap(MX28_USBCTRL1_BASE_AD=
DR, SZ_8K);
> + =C2=A0 =C2=A0 =C2=A0 if (ppriv->ctrl_regs =3D=3D NULL)
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 return -ENOMEM;
> +
> + =C2=A0 =C2=A0 =C2=A0 ppriv->usb_clk =3D clk_get(&pdev->dev, "usb1");
> + =C2=A0 =C2=A0 =C2=A0 if (IS_ERR(ppriv->usb_clk))
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 return PTR_ERR(ppriv->=
usb_clk);
> + =C2=A0 =C2=A0 =C2=A0 clk_enable(ppriv->usb_clk);
> +
> + =C2=A0 =C2=A0 =C2=A0 ppriv->usb_phy_clk =3D clk_get(&pdev->dev, "usb1_p=
hy");
> + =C2=A0 =C2=A0 =C2=A0 if (IS_ERR(ppriv->usb_phy_clk))
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 return PTR_ERR(ppriv->=
usb_phy_clk);
> + =C2=A0 =C2=A0 =C2=A0 clk_enable(ppriv->usb_phy_clk);
> +
> + =C2=A0 =C2=A0 =C2=A0 phy_clock_gate(ppriv, true);
> + =C2=A0 =C2=A0 =C2=A0 return fsl_usbh_init(pdev);
> +}
> +
> +static int fsl_usb_host_uninit(struct platform_device *pdev)
> +{
> + =C2=A0 =C2=A0 =C2=A0 struct mxc_usbh_platform_data *pdata =3D pdev->dev=
.platform_data;
> + =C2=A0 =C2=A0 =C2=A0 struct mxs_usb_private_date *ppriv =3D pdata->ppri=
v;
> +
> + =C2=A0 =C2=A0 =C2=A0 phy_clock_gate(ppriv, false);
> + =C2=A0 =C2=A0 =C2=A0 if (ppriv->usb_phy_clk) {
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 clk_disable(ppriv->usb=
_phy_clk);
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 clk_put(ppriv->usb_phy=
_clk);
> + =C2=A0 =C2=A0 =C2=A0 }
> + =C2=A0 =C2=A0 =C2=A0 if (ppriv->usb_clk) {
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 clk_disable(ppriv->usb=
_clk);
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 clk_put(ppriv->usb_clk=
);
> + =C2=A0 =C2=A0 =C2=A0 }
> + =C2=A0 =C2=A0 =C2=A0 if (ppriv->phy_regs)
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 iounmap(ppriv->phy_reg=
s);
> + =C2=A0 =C2=A0 =C2=A0 if (ppriv->ctrl_regs)
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 iounmap(ppriv->ctrl_re=
gs);
> +
> + =C2=A0 =C2=A0 =C2=A0 return 0;
> +}
> +
> +static struct mxs_usb_private_date usbh_private =3D {
> + =C2=A0 =C2=A0 =C2=A0 .internal_phy_clk_already_on =3D 0,
> +};
> +
> +static struct mxc_usbh_platform_data usbh_config =3D {
> + =C2=A0 =C2=A0 =C2=A0 .init =3D fsl_usb_host_init,
> + =C2=A0 =C2=A0 =C2=A0 .exit =3D fsl_usb_host_uninit,
> + =C2=A0 =C2=A0 =C2=A0 .portsc =3D MXC_EHCI_MODE_ULPI,
> + =C2=A0 =C2=A0 =C2=A0 .otg =3D NULL,
> + =C2=A0 =C2=A0 =C2=A0 .plt_irq_handler =3D fsl_plt_usbh_irq_handler,
> + =C2=A0 =C2=A0 =C2=A0 .ppriv =3D &usbh_private,
> +};
> +
> +/* The resources for kinds of usb devices */
> +static struct resource usbh_resources[] =3D {
> + =C2=A0 =C2=A0 =C2=A0 {
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 .start =3D MX28_USBCTR=
L1_BASE_ADDR,
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 .end =3D MX28_USBCTRL1=
_BASE_ADDR + 0x1ff,
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 .flags =3D IORESOURCE_=
MEM,
> + =C2=A0 =C2=A0 =C2=A0 },
> + =C2=A0 =C2=A0 =C2=A0 {
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 .start =3D MX28_INT_US=
B1,
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 .flags =3D IORESOURCE_=
IRQ,
> + =C2=A0 =C2=A0 =C2=A0 },
> +};
> +
> +static int __init usbh_init(void)
> +{
> + =C2=A0 =C2=A0 =C2=A0 struct platform_device *pdev;
> + =C2=A0 =C2=A0 =C2=A0 int instance_id =3D ~(u32) 0;
> + =C2=A0 =C2=A0 =C2=A0 u64 ehci_dmamask =3D ~(u32) 0;
> +
> + =C2=A0 =C2=A0 =C2=A0 if (!cpu_is_mx28())
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 return 0;
> +
> + =C2=A0 =C2=A0 =C2=A0 pdev =3D platform_device_register_resndata(NULL, "=
mxc-ehci", instance_id,
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =
=C2=A0 usbh_resources, ARRAY_SIZE(usbh_resources),
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =
=C2=A0 &usbh_config, sizeof(struct mxc_usbh_platform_data));
> + =C2=A0 =C2=A0 =C2=A0 if (IS_ERR(pdev)) {
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 pr_debug("can't regist=
er Host, %ld\n", PTR_ERR(pdev));
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 return PTR_ERR(pdev);
> + =C2=A0 =C2=A0 =C2=A0 }
> +
> + =C2=A0 =C2=A0 =C2=A0 pdev->dev.coherent_dma_mask =3D 0xffffffff;
> + =C2=A0 =C2=A0 =C2=A0 pdev->dev.dma_mask =3D &ehci_dmamask;
> +
> + =C2=A0 =C2=A0 =C2=A0 return 0;
> +}
> +module_init(usbh_init);
> diff --git a/arch/arm/mach-mxs/regs-usbphy-mx28.h b/arch/arm/mach-mxs/reg=
s-usbphy-mx28.h
> new file mode 100644
> index 0000000..2ec273b
> --- /dev/null
> +++ b/arch/arm/mach-mxs/regs-usbphy-mx28.h
> @@ -0,0 +1,240 @@
> +/*
> + * Freescale USBPHY Register Definitions
> + *
> + * Copyright 2008-2011 Freescale Semiconductor, Inc. All Rights Reserved=
.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. =C2=A0See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA =C2=A002111-=
1307 USA
> + *
> + *
> + * Xml Revision: 1.52
> + * Template revision: 26195
> + */
> +
> +#ifndef __ARCH_ARM___USBPHY_H
> +#define __ARCH_ARM___USBPHY_H
> +
> +
> +#define HW_USBPHY_PWD =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A00x00000000
> +#define HW_USBPHY_PWD_SET =C2=A0 =C2=A0 =C2=A00x00000004
> +#define HW_USBPHY_PWD_CLR =C2=A0 =C2=A0 =C2=A00x00000008
> +#define HW_USBPHY_PWD_TOG =C2=A0 =C2=A0 =C2=A00x0000000c
> +
> +#define BM_USBPHY_PWD_RXPWDRX =C2=A00x00100000
> +#define BM_USBPHY_PWD_RXPWDDIFF =C2=A0 =C2=A0 =C2=A0 =C2=A00x00080000
> +#define BM_USBPHY_PWD_RXPWD1PT1 =C2=A0 =C2=A0 =C2=A0 =C2=A00x00040000
> +#define BM_USBPHY_PWD_RXPWDENV 0x00020000
> +
> +#define BM_USBPHY_PWD_TXPWDV2I 0x00001000
> +#define BM_USBPHY_PWD_TXPWDIBIAS =C2=A0 =C2=A0 =C2=A0 0x00000800
> +#define BM_USBPHY_PWD_TXPWDFS =C2=A00x00000400
> +
> +#define HW_USBPHY_TX =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 0x00000010
> +#define HW_USBPHY_TX_SET =C2=A0 =C2=A0 =C2=A0 0x00000014
> +#define HW_USBPHY_TX_CLR =C2=A0 =C2=A0 =C2=A0 0x00000018
> +#define HW_USBPHY_TX_TOG =C2=A0 =C2=A0 =C2=A0 0x0000001c
> +
> +#define BP_USBPHY_TX_USBPHY_TX_EDGECTRL =C2=A0 =C2=A0 =C2=A0 =C2=A026
> +#define BM_USBPHY_TX_USBPHY_TX_EDGECTRL =C2=A0 =C2=A0 =C2=A0 =C2=A00x1C0=
00000
> +#define BF_USBPHY_TX_USBPHY_TX_EDGECTRL(v) =C2=A0\
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (((v) << 26) & BM_USBP=
HY_TX_USBPHY_TX_EDGECTRL)
> +#define BM_USBPHY_TX_USBPHY_TX_SYNC_INVERT =C2=A0 =C2=A0 0x02000000
> +#define BM_USBPHY_TX_USBPHY_TX_SYNC_MUX =C2=A0 =C2=A0 =C2=A0 =C2=A00x010=
00000
> +
> +#define BM_USBPHY_TX_TXENCAL45DP =C2=A0 =C2=A0 =C2=A0 0x00200000
> +#define BP_USBPHY_TX_TXCAL45DP 16
> +#define BM_USBPHY_TX_TXCAL45DP 0x000F0000
> +#define BF_USBPHY_TX_TXCAL45DP(v) =C2=A0\
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (((v) << 16) & BM_USBP=
HY_TX_TXCAL45DP)
> +#define BM_USBPHY_TX_TXENCAL45DN =C2=A0 =C2=A0 =C2=A0 0x00002000
> +#define BP_USBPHY_TX_TXCAL45DN 8
> +#define BM_USBPHY_TX_TXCAL45DN 0x00000F00
> +#define BF_USBPHY_TX_TXCAL45DN(v) =C2=A0\
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (((v) << 8) & BM_USBPH=
Y_TX_TXCAL45DN)
> +
> +#define BP_USBPHY_TX_D_CAL =C2=A0 =C2=A0 0
> +#define BM_USBPHY_TX_D_CAL =C2=A0 =C2=A0 0x0000000F
> +#define BF_USBPHY_TX_D_CAL(v) =C2=A0\
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (((v) << 0) & BM_USBPH=
Y_TX_D_CAL)
> +
> +#define HW_USBPHY_RX =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 0x00000020
> +#define HW_USBPHY_RX_SET =C2=A0 =C2=A0 =C2=A0 0x00000024
> +#define HW_USBPHY_RX_CLR =C2=A0 =C2=A0 =C2=A0 0x00000028
> +#define HW_USBPHY_RX_TOG =C2=A0 =C2=A0 =C2=A0 0x0000002c
> +
> +#define BM_USBPHY_RX_RXDBYPASS 0x00400000
> +#define BP_USBPHY_RX_DISCONADJ 4
> +#define BM_USBPHY_RX_DISCONADJ 0x00000070
> +#define BF_USBPHY_RX_DISCONADJ(v) =C2=A0\
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (((v) << 4) & BM_USBPH=
Y_RX_DISCONADJ)
> +#define BP_USBPHY_RX_ENVADJ =C2=A0 =C2=A00
> +#define BM_USBPHY_RX_ENVADJ =C2=A0 =C2=A00x00000007
> +#define BF_USBPHY_RX_ENVADJ(v) =C2=A0\
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (((v) << 0) & BM_USBPH=
Y_RX_ENVADJ)
> +
> +#define HW_USBPHY_CTRL =C2=A0 =C2=A0 =C2=A0 =C2=A0 0x00000030
> +#define HW_USBPHY_CTRL_SET =C2=A0 =C2=A0 0x00000034
> +#define HW_USBPHY_CTRL_CLR =C2=A0 =C2=A0 0x00000038
> +#define HW_USBPHY_CTRL_TOG =C2=A0 =C2=A0 0x0000003c
> +
> +#define BM_USBPHY_CTRL_SFTRST =C2=A00x80000000
> +#define BM_USBPHY_CTRL_CLKGATE 0x40000000
> +#define BM_USBPHY_CTRL_UTMI_SUSPENDM =C2=A0 0x20000000
> +#define BM_USBPHY_CTRL_HOST_FORCE_LS_SE0 =C2=A0 =C2=A0 =C2=A0 0x10000000
> +#define BM_USBPHY_CTRL_ENAUTOSET_USBCLKS =C2=A0 =C2=A0 =C2=A0 0x04000000
> +#define BM_USBPHY_CTRL_ENAUTOCLR_USBCLKGATE =C2=A0 =C2=A00x02000000
> +#define BM_USBPHY_CTRL_FSDLL_RST_EN =C2=A0 =C2=A00x01000000
> +#define BM_USBPHY_CTRL_ENVBUSCHG_WKUP =C2=A00x00800000
> +#define BM_USBPHY_CTRL_ENIDCHG_WKUP =C2=A0 =C2=A00x00400000
> +#define BM_USBPHY_CTRL_ENDPDMCHG_WKUP =C2=A00x00200000
> +#define BM_USBPHY_CTRL_ENAUTOCLR_PHY_PWD =C2=A0 =C2=A0 =C2=A0 0x00100000
> +#define BM_USBPHY_CTRL_ENAUTOCLR_CLKGATE =C2=A0 =C2=A0 =C2=A0 0x00080000
> +#define BM_USBPHY_CTRL_ENAUTO_PWRON_PLL =C2=A0 =C2=A0 =C2=A0 =C2=A00x000=
40000
> +#define BM_USBPHY_CTRL_WAKEUP_IRQ =C2=A0 =C2=A0 =C2=A00x00020000
> +#define BM_USBPHY_CTRL_ENIRQWAKEUP =C2=A0 =C2=A0 0x00010000
> +#define BM_USBPHY_CTRL_ENUTMILEVEL3 =C2=A0 =C2=A00x00008000
> +#define BM_USBPHY_CTRL_ENUTMILEVEL2 =C2=A0 =C2=A00x00004000
> +#define BM_USBPHY_CTRL_DATA_ON_LRADC =C2=A0 0x00002000
> +#define BM_USBPHY_CTRL_DEVPLUGIN_IRQ =C2=A0 0x00001000
> +#define BM_USBPHY_CTRL_ENIRQDEVPLUGIN =C2=A00x00000800
> +#define BM_USBPHY_CTRL_RESUME_IRQ =C2=A0 =C2=A0 =C2=A00x00000400
> +#define BM_USBPHY_CTRL_ENIRQRESUMEDETECT =C2=A0 =C2=A0 =C2=A0 0x00000200
> +#define BM_USBPHY_CTRL_RESUMEIRQSTICKY 0x00000100
> +#define BM_USBPHY_CTRL_ENOTGIDDETECT =C2=A0 0x00000080
> +#define BM_USBPHY_CTRL_DEVPLUGIN_POLARITY =C2=A0 =C2=A0 =C2=A00x00000020
> +#define BM_USBPHY_CTRL_ENDEVPLUGINDETECT =C2=A0 =C2=A0 =C2=A0 0x00000010
> +#define BM_USBPHY_CTRL_HOSTDISCONDETECT_IRQ =C2=A0 =C2=A00x00000008
> +#define BM_USBPHY_CTRL_ENIRQHOSTDISCON 0x00000004
> +#define BM_USBPHY_CTRL_ENHOSTDISCONDETECT =C2=A0 =C2=A0 =C2=A00x00000002
> +
> +#define HW_USBPHY_STATUS =C2=A0 =C2=A0 =C2=A0 0x00000040
> +
> +#define BM_USBPHY_STATUS_RESUME_STATUS 0x00000400
> +#define BM_USBPHY_STATUS_OTGID_STATUS =C2=A00x00000100
> +#define BM_USBPHY_STATUS_DEVPLUGIN_STATUS =C2=A0 =C2=A0 =C2=A00x00000040
> +#define BM_USBPHY_STATUS_HOSTDISCONDETECT_STATUS =C2=A0 =C2=A0 =C2=A0 0x=
00000008
> +
> +#define HW_USBPHY_DEBUG =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0=
=C2=A00x00000050
> +#define HW_USBPHY_DEBUG_SET =C2=A0 =C2=A00x00000054
> +#define HW_USBPHY_DEBUG_CLR =C2=A0 =C2=A00x00000058
> +#define HW_USBPHY_DEBUG_TOG =C2=A0 =C2=A00x0000005c
> +
> +#define BM_USBPHY_DEBUG_CLKGATE =C2=A0 =C2=A0 =C2=A0 =C2=A00x40000000
> +#define BM_USBPHY_DEBUG_HOST_RESUME_DEBUG =C2=A0 =C2=A0 =C2=A00x20000000
> +#define BP_USBPHY_DEBUG_SQUELCHRESETLENGTH =C2=A0 =C2=A0 25
> +#define BM_USBPHY_DEBUG_SQUELCHRESETLENGTH =C2=A0 =C2=A0 0x1E000000
> +#define BF_USBPHY_DEBUG_SQUELCHRESETLENGTH(v) =C2=A0\
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (((v) << 25) & BM_USBP=
HY_DEBUG_SQUELCHRESETLENGTH)
> +#define BM_USBPHY_DEBUG_ENSQUELCHRESET 0x01000000
> +#define BP_USBPHY_DEBUG_SQUELCHRESETCOUNT =C2=A0 =C2=A0 =C2=A016
> +#define BM_USBPHY_DEBUG_SQUELCHRESETCOUNT =C2=A0 =C2=A0 =C2=A00x001F0000
> +#define BF_USBPHY_DEBUG_SQUELCHRESETCOUNT(v) =C2=A0\
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (((v) << 16) & BM_USBP=
HY_DEBUG_SQUELCHRESETCOUNT)
> +#define BM_USBPHY_DEBUG_ENTX2RXCOUNT =C2=A0 0x00001000
> +#define BP_USBPHY_DEBUG_TX2RXCOUNT =C2=A0 =C2=A0 8
> +#define BM_USBPHY_DEBUG_TX2RXCOUNT =C2=A0 =C2=A0 0x00000F00
> +#define BF_USBPHY_DEBUG_TX2RXCOUNT(v) =C2=A0\
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (((v) << 8) & BM_USBPH=
Y_DEBUG_TX2RXCOUNT)
> +#define BP_USBPHY_DEBUG_ENHSTPULLDOWN =C2=A04
> +#define BM_USBPHY_DEBUG_ENHSTPULLDOWN =C2=A00x00000030
> +#define BF_USBPHY_DEBUG_ENHSTPULLDOWN(v) =C2=A0\
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (((v) << 4) & BM_USBPH=
Y_DEBUG_ENHSTPULLDOWN)
> +#define BP_USBPHY_DEBUG_HSTPULLDOWN =C2=A0 =C2=A02
> +#define BM_USBPHY_DEBUG_HSTPULLDOWN =C2=A0 =C2=A00x0000000C
> +#define BF_USBPHY_DEBUG_HSTPULLDOWN(v) =C2=A0\
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (((v) << 2) & BM_USBPH=
Y_DEBUG_HSTPULLDOWN)
> +#define BM_USBPHY_DEBUG_DEBUG_INTERFACE_HOLD =C2=A0 0x00000002
> +#define BM_USBPHY_DEBUG_OTGIDPIOLOCK =C2=A0 0x00000001
> +
> +#define HW_USBPHY_DEBUG0_STATUS =C2=A0 =C2=A0 =C2=A0 =C2=A00x00000060
> +
> +#define BP_USBPHY_DEBUG0_STATUS_SQUELCH_COUNT =C2=A026
> +#define BM_USBPHY_DEBUG0_STATUS_SQUELCH_COUNT =C2=A00xFC000000
> +#define BF_USBPHY_DEBUG0_STATUS_SQUELCH_COUNT(v) \
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (((v) << 26) & BM_USBP=
HY_DEBUG0_STATUS_SQUELCH_COUNT)
> +#define BP_USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT =C2=A0 =C2=A0 =
=C2=A0 =C2=A016
> +#define BM_USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT =C2=A0 =C2=A0 =
=C2=A0 =C2=A00x03FF0000
> +#define BF_USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT(v) =C2=A0\
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (((v) << 16) & BM_USBP=
HY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT)
> +#define BP_USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT =C2=A0 0
> +#define BM_USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT =C2=A0 0x0000FFFF
> +#define BF_USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT(v) =C2=A0\
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (((v) << 0) & BM_USBPH=
Y_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT)
> +
> +#define HW_USBPHY_DEBUG1 =C2=A0 =C2=A0 =C2=A0 0x00000070
> +#define HW_USBPHY_DEBUG1_SET =C2=A0 0x00000074
> +#define HW_USBPHY_DEBUG1_CLR =C2=A0 0x00000078
> +#define HW_USBPHY_DEBUG1_TOG =C2=A0 0x0000007c
> +
> +#define BP_USBPHY_DEBUG1_ENTAILADJVD =C2=A0 13
> +#define BM_USBPHY_DEBUG1_ENTAILADJVD =C2=A0 0x00006000
> +#define BF_USBPHY_DEBUG1_ENTAILADJVD(v) =C2=A0\
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (((v) << 13) & BM_USBP=
HY_DEBUG1_ENTAILADJVD)
> +#define BM_USBPHY_DEBUG1_ENTX2TX =C2=A0 =C2=A0 =C2=A0 0x00001000
> +#define BP_USBPHY_DEBUG1_DBG_ADDRESS =C2=A0 0
> +#define BM_USBPHY_DEBUG1_DBG_ADDRESS =C2=A0 0x0000000F
> +#define BF_USBPHY_DEBUG1_DBG_ADDRESS(v) =C2=A0\
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (((v) << 0) & BM_USBPH=
Y_DEBUG1_DBG_ADDRESS)
> +
> +#define HW_USBPHY_VERSION =C2=A0 =C2=A0 =C2=A00x00000080
> +
> +#define BP_USBPHY_VERSION_MAJOR =C2=A0 =C2=A0 =C2=A0 =C2=A024
> +#define BM_USBPHY_VERSION_MAJOR =C2=A0 =C2=A0 =C2=A0 =C2=A00xFF000000
> +#define BF_USBPHY_VERSION_MAJOR(v) \
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (((v) << 24) & BM_USBP=
HY_VERSION_MAJOR)
> +#define BP_USBPHY_VERSION_MINOR =C2=A0 =C2=A0 =C2=A0 =C2=A016
> +#define BM_USBPHY_VERSION_MINOR =C2=A0 =C2=A0 =C2=A0 =C2=A00x00FF0000
> +#define BF_USBPHY_VERSION_MINOR(v) =C2=A0\
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (((v) << 16) & BM_USBP=
HY_VERSION_MINOR)
> +#define BP_USBPHY_VERSION_STEP 0
> +#define BM_USBPHY_VERSION_STEP 0x0000FFFF
> +#define BF_USBPHY_VERSION_STEP(v) =C2=A0\
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (((v) << 0) & BM_USBPH=
Y_VERSION_STEP)
> +
> +#define HW_USBPHY_IP =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 0x00000090
> +#define HW_USBPHY_IP_SET =C2=A0 =C2=A0 =C2=A0 0x00000094
> +#define HW_USBPHY_IP_CLR =C2=A0 =C2=A0 =C2=A0 0x00000098
> +#define HW_USBPHY_IP_TOG =C2=A0 =C2=A0 =C2=A0 0x0000009c
> +
> +#define BP_USBPHY_IP_DIV_SEL =C2=A0 23
> +#define BM_USBPHY_IP_DIV_SEL =C2=A0 0x01800000
> +#define BF_USBPHY_IP_DIV_SEL(v) =C2=A0\
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (((v) << 23) & BM_USBP=
HY_IP_DIV_SEL)
> +#define BV_USBPHY_IP_DIV_SEL__DEFAULT =C2=A0 0x0
> +#define BV_USBPHY_IP_DIV_SEL__LOWER =C2=A0 =C2=A0 0x1
> +#define BV_USBPHY_IP_DIV_SEL__LOWEST =C2=A0 =C2=A00x2
> +#define BV_USBPHY_IP_DIV_SEL__UNDEFINED 0x3
> +#define BP_USBPHY_IP_LFR_SEL =C2=A0 21
> +#define BM_USBPHY_IP_LFR_SEL =C2=A0 0x00600000
> +#define BF_USBPHY_IP_LFR_SEL(v) =C2=A0\
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (((v) << 21) & BM_USBP=
HY_IP_LFR_SEL)
> +#define BV_USBPHY_IP_LFR_SEL__DEFAULT =C2=A0 0x0
> +#define BV_USBPHY_IP_LFR_SEL__TIMES_2 =C2=A0 0x1
> +#define BV_USBPHY_IP_LFR_SEL__TIMES_05 =C2=A00x2
> +#define BV_USBPHY_IP_LFR_SEL__UNDEFINED 0x3
> +#define BP_USBPHY_IP_CP_SEL =C2=A0 =C2=A019
> +#define BM_USBPHY_IP_CP_SEL =C2=A0 =C2=A00x00180000
> +#define BF_USBPHY_IP_CP_SEL(v) =C2=A0\
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (((v) << 19) & BM_USBP=
HY_IP_CP_SEL)
> +#define BV_USBPHY_IP_CP_SEL__DEFAULT =C2=A0 0x0
> +#define BV_USBPHY_IP_CP_SEL__TIMES_2 =C2=A0 0x1
> +#define BV_USBPHY_IP_CP_SEL__TIMES_05 =C2=A00x2
> +#define BV_USBPHY_IP_CP_SEL__UNDEFINED 0x3
> +#define BM_USBPHY_IP_TSTI_TX_DP =C2=A0 =C2=A0 =C2=A0 =C2=A00x00040000
> +#define BM_USBPHY_IP_TSTI_TX_DM =C2=A0 =C2=A0 =C2=A0 =C2=A00x00020000
> +#define BM_USBPHY_IP_ANALOG_TESTMODE =C2=A0 0x00010000
> +#define BM_USBPHY_IP_EN_USB_CLKS =C2=A0 =C2=A0 =C2=A0 0x00000004
> +#define BM_USBPHY_IP_PLL_LOCKED =C2=A0 =C2=A0 =C2=A0 =C2=A00x00000002
> +#define BM_USBPHY_IP_PLL_POWER 0x00000001
> +#endif /* __ARCH_ARM___USBPHY_H */
> --
> 1.7.0.4
>
>
>
More information about the linux-arm-kernel
mailing list