[PATCH 2a/5] Remove unsafe clock values from omap1_defconfig

[Tony Lindgren]

* Janusz Krzysztofik <jkrzyszt at tis.icnet.pl> [111201 10:04]:
> On Thursday 01 of December 2011 at 18:17:58, Tony Lindgren wrote:
> > 
> > --- a/arch/arm/mach-omap1/clock_data.c
> > +++ b/arch/arm/mach-omap1/clock_data.c
> > @@ -927,7 +927,7 @@ int __init omap1_clk_init(void)
> >  
> >  void __init omap1_clk_late_init(void)
> >  {
> > -	if (ck_dpll1.rate >= OMAP1_DPLL1_SANE_VALUE)
> > +	if (ck_dpll1.rate > OMAP1_DPLL1_SANE_VALUE)
> >  		return;
> >  
> >  	/* Find the highest supported frequency and enable it */
> 
> This change really makes sense to me, however, knowing the initial 
> (bootloader selected) clock rate my board boots at, which is 
> unfortunately raw 12 MHz, I would be surprised if that helped.

OK, that's not it then. BTW, we should be able to drop that test once
we have your patches applied.
 
> Before e9b7086b80c4d9e354f4edc9e280ae85a60df408, 
> omap1_select_table_rate() was returning the rate selected with .config 
> because it was called early, with ck_dpll1_p->rate uninitialized. Now it 
> is not, and returns nothing, resulting in 60 MHz default. Then, the only 
> way I can see to correct the problem is something like patch 3/5, which 
> you are justifiably affraid of of always switching to 216 MHz with 
> omap1_defconfig.

Ah, you got it! That's what causes the regression. How about the following
fix for the -rc cycle then?

Tony


From: Tony Lindgren <tony at atomide.com>
Date: Thu, 1 Dec 2011 11:00:11 -0800
Subject: [PATCH] ARM: OMAP1: Fix reprogramming of DPLL1 for systems that boot at rates below 60MHz

Commit e9b7086b80c4d9e354f4edc9e280ae85a60df408 (ARM: OMAP: Fix
reprogramming of dpll1 rate) fixed a regression for systems that
did not rely on bootloader set rates.

However, it also introduced a new problem where the rates selected
in .config would not take affect as omap1_select_table_rate
currently refuses to reprogram DPLL1 if it's already initialized.

This was not a problem earlier, as the reprogramming was done
earlier with ck_dpll1_p->rate uninitialized.

Fix this by forcing the reprogramming on systems booting at rates
below 60MHz. Note that the long term fix is to make the rates
SoC specific later on.

Thanks for Janusz Krzysztofik <jkrzyszt at tis.icnet.pl> for figuring
this one out.

Reported-by: Janusz Krzysztofik <jkrzyszt at tis.icnet.pl>
Signed-off-by: Tony Lindgren <tony at atomide.com>

diff --git a/arch/arm/mach-omap1/clock_data.c b/arch/arm/mach-omap1/clock_data.c
index 1297bb5..3f30561 100644
--- a/arch/arm/mach-omap1/clock_data.c
+++ b/arch/arm/mach-omap1/clock_data.c
@@ -930,6 +930,9 @@ void __init omap1_clk_late_init(void)
 	if (ck_dpll1.rate >= OMAP1_DPLL1_SANE_VALUE)
 		return;
 
+	/* System booting at unusable rate, force reprogramming of DPLL1 */
+	ck_dpll1_p->rate = 0;
+
 	/* Find the highest supported frequency and enable it */
 	if (omap1_select_table_rate(&virtual_ck_mpu, ~0)) {
 		pr_err("System frequencies not set, using default. Check your config.\n");