[PATCH 43/74] ST SPEAr : EMI (Extrenal Memory Interface) controller driver
Jean-Christophe PLAGNIOL-VILLARD
plagnioj at jcrosoft.com
Fri Sep 10 05:21:13 EDT 2010
On 14:36 Fri 10 Sep , Vipin Kumar wrote:
> On 9/10/2010 2:26 PM, Jean-Christophe PLAGNIOL-VILLARD wrote:
> > On 13:41 Fri 10 Sep , Vipin Kumar wrote:
> >> On 9/7/2010 7:02 PM, Jean-Christophe PLAGNIOL-VILLARD wrote:
> >>> On 17:24 Tue 07 Sep , viresh kumar wrote:
> >>>> On 9/7/2010 5:08 PM, Jean-Christophe PLAGNIOL-VILLARD wrote:
> >>>>>>>> +/* emi nor flash device registeration */
> >>>>>>>>>>>>> +static struct physmap_flash_data emi_norflash_data;
> >>>>>>>>>>>>> +
> >>>>>>>>>>>>> +static struct resource emi_nor_resources[] = {
> >>>>>>>>>>>>> + {
> >>>>>>>>>>>>> + .start = SPEAR310_EMI_MEM_0_BASE,
> >>>>>>>>>>>>> + .end = SPEAR310_EMI_MEM_0_BASE + SPEAR310_EMI_MEM_SIZE - 1,
> >>>>>>>>>>>>> + .flags = IORESOURCE_MEM,
> >>>>>>>>>>>>> + },
> >>>>>>>>>>>>> +};
> >>>>>>>>> it's board specfic not mach
> >>>>>>>>>
> >>>>>>>>> NACK
> >>>>>>>
> >>>>>>> No. This is machine specific. Same for all boards.
> >>>>> NACK as you can have a flash at other place and more than one flash
> >>>>> and the size depend on the flash
> >>>>
> >>>> Correct!! Size has to be board specific. Will modify it.
> >>> and the start also as you may have 2 nor flash on different bank
> >>>
> >>
> >> The start addresses in our case are fixed for a particular bank.
> > but not for the nor so let this decide by every board
> > not by the SoC
> >
>
> The NOR memory is placed within the system memory address space.
> For NAND offourse, it lies beyond system space.
>
> EMI is a Parallel NOR memory controller and the base address and
> maximum size of each bank is fixed in our system...
but the then is not necessarely at bank 0
Best Regards,
J.
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