[PATCH 04/13] clk: amlogic: Add basic clock driver

[Chuan Liu]

Hi Krzysztof,


On 4/9/2026 2:12 PM, Krzysztof Kozlowski wrote:
> [ EXTERNAL EMAIL ]
> 
> On 08/04/2026 16:32, Chuan Liu wrote:
>> Hi Krzysztof (& ALL),
>> Thanks for review.
>>
>> On 2/9/2026 9:17 PM, Krzysztof Kozlowski wrote:
>>> [ EXTERNAL EMAIL ]
>>>
>>> On 09/02/2026 06:48, Chuan Liu via B4 Relay wrote:
>>>> From: Chuan Liu <chuan.liu at amlogic.com>
>>>>
>>>> Implement core clock driver for Amlogic SoC platforms, supporting
>>>
>>> So how did all existing Amlogic SoC platforms work so far without basic
>>> clock driver? Really, how?
>>>
>>> You are suppose to grow existing code, not add your completely new
>>> "basic" driver just because you have it that way in downstream.
>>>
>>
>> Firstly, apologies for the delayed response. I had intended to
>> consolidate the V1 review feedback and come back with a clearer plan for
>> V2 changes. In the meantime, Martin has provided many detailed and
>> valuable suggestions - much appreciated.
>>
>> The original goal of optimizing the HW based on A9 and introducing a new
>> clock driver is to reduce unnecessary complexity in the driver. On A9,
> 
> Nah, you just don't care about upstream and it is easier for you to
> duplicate new code.

Regarding the "duplicate new code": the ops implemented in clk-basic.c 
are indeed based on the CCF components (clk-mux, clk-divider, clk-gate), 
with the following enhancements:
   - Register access via regmap (meson clock driver looks like this)
   - Additional debug nodes to support Amlogic clock automated test 
tools (in conjunction with clk-measure to verify hardware functionality 
of each clock)
   - Clock context save/restore support for STD/STR

Other drivers mainly focus on adapting to A9-specific hardware 
optimizations, as well as improving and refactoring the existing meson 
drivers.

> 
>> we optimized the Clock/PLL controller HW to simplify driver performance,
>> complexity, memory footprint, and reusability. Improvements on the HW
>> side can also help drive corresponding enhancements in the driver:
>>      - Performance: Encapsulates sub-clock functions, reducing call paths
>>      - Complexity: Standardized register bits eliminate a large number of
>> bit definitions (~1/3 of original code is defined register bit [1])
>>      - Memory: Object-oriented design avoids copy/paste for repeated clocks
> 
> Object oriented design? Sorry, what?

In the new driver, clocks are modeled as the SoC CCU itself. For 
example, pwm_a/b/c... and emmc_a/b/c use the same CCU, represented as a 
"composite-ccu". We instantiate the CCU once, rather than redefining 
clocks for each module.

> 
>>      - Reusability: Same controller works across SoCs without driver
>> changes (or with minimal changes)
>>
>> The old meson driver required compromises to unify legacy controller
>> characteristics and driver styles. On A9, we want a fresh start.
> 
> And maintainers don't want that. We expressed this many times already.
> Not only in this thread - that's one of the most known feedbacks.

Thanks for the clarification.

> 
> Best regards,
> Krzysztof

-- 
Best regards,
Chuan