[openwrt/openwrt] ramips: mt7620: fix RGMII TXID PHY mode

[LEDE Commits]

981213 pushed a commit to openwrt/openwrt.git, branch master:
https://git.openwrt.org/26c84b2e46caba1ae17bc82a533c99eee65e7004

commit 26c84b2e46caba1ae17bc82a533c99eee65e7004
Author: Michael Pratt <mcpratt at pm.me>
AuthorDate: Sat May 1 14:17:11 2021 -0400

    ramips: mt7620: fix RGMII TXID PHY mode
    
    the register bits for TX delay and RX delay are opposites:
    when TX delay bit is set, delay is enabled
    when RX delay bit is set, delay is disabled
    
    So, when both bits are unset, it is RX delay
    and when both bits are set, it is TX delay
    
    Note: TXID is the default RGMII mode of the SOC
    
    Fixes: 5410a8e2959a ("ramips: mt7620: add rgmii delays support")
    Signed-off-by: Michael Pratt <mcpratt at pm.me>
---
 target/linux/ramips/files/drivers/net/ethernet/ralink/soc_mt7620.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/linux/ramips/files/drivers/net/ethernet/ralink/soc_mt7620.c b/target/linux/ramips/files/drivers/net/ethernet/ralink/soc_mt7620.c
index 4d012afa14..c9104aa375 100644
--- a/target/linux/ramips/files/drivers/net/ethernet/ralink/soc_mt7620.c
+++ b/target/linux/ramips/files/drivers/net/ethernet/ralink/soc_mt7620.c
@@ -205,7 +205,7 @@ static void mt7620_port_init(struct fe_priv *priv, struct device_node *np)
 		break;
 	case PHY_INTERFACE_MODE_RGMII_TXID:
 		mask = 0;
-		val_delay &= ~GSW_REG_GPCx_TXDELAY;
+		val_delay |= GSW_REG_GPCx_TXDELAY;
 		val_delay |= GSW_REG_GPCx_RXDELAY;
 		break;
 	case PHY_INTERFACE_MODE_MII: