[PATCH v3] spi: rockchip: initialize bus_num to -1

[Ahmad Fatoum]

Hi,

On 8/27/26 2:06 PM, support wrote:
> Applied, thanks!  

I have no idea what this is.

Before pointing a bot that can send email at the mailing list, please
start a (human) discussion about what you are think this accomplishes.

Also generally this style of mails is not acceptable. It confuses users
to say you apply patches (apply where?) and the formatting is broken.

Ahmad

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> Thanks for the quick turnaround on this one. This bug class is more common than the MNT report suggests — any RK3588/RK3568 board 
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> design with a PMIC on one SPI controller and peripherals on another (which is the standard topology for RK806-based designs, 
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> e.g. our own boards with the PMIC on SPI2) hits the same bus_num=0 collision the moment a second controller is enabled. 
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> So far most of these designs simply never enabled two controllers in barebox, which is probably why it stayed latent this long. 
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> One observation on the failure mode itself: the XFM_RO while(1) hang in rockchip_spi_pio is a separate latent hazard. Even with bus routing now correct, 
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> any future misrouted or wrong-device read can still wedge the bootloader with no timeout and no diagnostic output. 
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> Might be worth a follow-up hardening patch — a transfer timeout in the PIO loop would turn a silent hang into a loud error at the cost of a few lines.
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> We're tracking this fix for our RK35xx barebox evaluation (secure boot path for industrial designs), so it's on the regression checklist for the next release.
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>  --Boardcon Embedded Design — Rockchip-based industrial SBCs & SoMs
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> https://www.boardcon.com
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