[PATCH 3/9] arm: socfpga: agilex5: configure firewall with base and size

[Michael Tretter]

The firewall configuration internally uses the DDR base address and
reserves some space for the TF-A. Pass the base address of the region 0
as a parameter to make it more visible.

Since base is now the base of region 0 instead of the DDR base, the
passed size must now be the size of region 0 instead of the full DDR
size.

Signed-off-by: Michael Tretter <m.tretter at pengutronix.de>
---
 arch/arm/mach-socfpga/agilex5-sdram.c | 27 +++++++++++----------------
 1 file changed, 11 insertions(+), 16 deletions(-)

diff --git a/arch/arm/mach-socfpga/agilex5-sdram.c b/arch/arm/mach-socfpga/agilex5-sdram.c
index 4e7994985d26..4d95c7b64306 100644
--- a/arch/arm/mach-socfpga/agilex5-sdram.c
+++ b/arch/arm/mach-socfpga/agilex5-sdram.c
@@ -179,20 +179,14 @@ static bool ddr_ecc_dbe_status(void)
 	return false;
 }
 
-static void sdram_set_firewall(phys_size_t hw_size)
+static void sdram_set_firewall(phys_addr_t base, phys_size_t size)
 {
-	phys_size_t value;
+	phys_addr_t limit = base + size - 1;
 	u32 lower, upper;
 
-	value = SOCFPGA_AGILEX5_DDR_BASE;
-	/* Keep first 1MB of SDRAM memory region as secure region when
-	 * using ATF flow, where the ATF code is located.
-	 */
-	value += SZ_1M;
-
 	/* Setting non-secure MPU region base and base extended */
-	lower = lower_32_bits(value);
-	upper = upper_32_bits(value);
+	lower = lower_32_bits(base);
+	upper = upper_32_bits(base);
 	FW_MPU_DDR_SCR_WRITEL(lower, FW_MPU_DDR_SCR_MPUREGION0ADDR_BASE);
 	FW_MPU_DDR_SCR_WRITEL(upper & 0xff, FW_MPU_DDR_SCR_MPUREGION0ADDR_BASEEXT);
 	FW_F2SDRAM_DDR_SCR_WRITEL(lower, FW_F2SDRAM_DDR_SCR_REGION0ADDR_BASE);
@@ -203,11 +197,8 @@ static void sdram_set_firewall(phys_size_t hw_size)
 	FW_MPU_DDR_SCR_WRITEL(upper & 0xff, FW_MPU_DDR_SCR_NONMPUREGION0ADDR_BASEEXT);
 
 	/* Setting non-secure MPU limit and limit extended */
-	value = SOCFPGA_AGILEX5_DDR_BASE + hw_size - 1;
-
-	lower = lower_32_bits(value);
-	upper = upper_32_bits(value);
-
+	lower = lower_32_bits(limit);
+	upper = upper_32_bits(limit);
 	FW_MPU_DDR_SCR_WRITEL(lower, FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMIT);
 	FW_MPU_DDR_SCR_WRITEL(upper & 0xff, FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMITEXT);
 
@@ -327,7 +318,11 @@ int agilex5_ddr_init_full(void)
 		hw_size -= hw_size / 8;
 	pr_debug("%s: %lld MiB\n", io96b_ctrl.ddr_type, hw_size / SZ_1M);
 
-	sdram_set_firewall(hw_size);
+	/*
+	 * Keep first 1MB of SDRAM memory region as secure region when
+	 * using ATF flow, where the ATF code is located.
+	 */
+	sdram_set_firewall(SOCFPGA_AGILEX5_DDR_BASE + SZ_1M, hw_size - SZ_1M);
 
 	/* Firewall setting for MPFE CSR */
 	/* IO96B0_reg */

-- 
2.47.3