[PATCH 07/16] ata: ahci: correct named constants values and names

[Denis Orlov]

This gives more clear names to some of the macros that designate the
sizes of various memory structures and fixes a mistake in one of them.
The command table item was regarded as taking 32 bytes in size while
it is actually supposed to only take 16 bytes according to the spec.
This also changes a somewhat misleading comment that calls the command
list a command table. There is a cmt_tbl field that actually holds a
pointer to a different structure that is called a command table in the
specification, so it seems better to more clearly disambiguate them.

Signed-off-by: Denis Orlov <denorl2009 at gmail.com>
---
 drivers/ata/ahci.c |  6 +++---
 drivers/ata/ahci.h | 10 ++++++----
 2 files changed, 9 insertions(+), 7 deletions(-)

diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
index c02f499ac1..f7eb35c09d 100644
--- a/drivers/ata/ahci.c
+++ b/drivers/ata/ahci.c
@@ -288,10 +288,10 @@ static int ahci_init_port(struct ahci_port *ahci_port)
 	}
 
 	/*
-	 * First item in chunk of DMA memory: 32-slot command table,
+	 * First item in chunk of DMA memory: 32-slot command list,
 	 * 32 bytes each in size
 	 */
-	ahci_port->cmd_slot = dma_alloc_coherent(AHCI_CMD_SLOT_SZ * 32,
+	ahci_port->cmd_slot = dma_alloc_coherent(AHCI_CMD_LIST_SZ,
 						  &ahci_port->cmd_slot_dma);
 	if (!ahci_port->cmd_slot) {
 		ret = -ENOMEM;
@@ -419,7 +419,7 @@ err_alloc2:
 			  AHCI_RX_FIS_SZ);
 err_alloc1:
 	dma_free_coherent(ahci_port->cmd_slot, ahci_port->cmd_slot_dma,
-			  AHCI_CMD_SLOT_SZ * 32);
+			  AHCI_CMD_LIST_SZ);
 err_alloc:
 	return ret;
 }
diff --git a/drivers/ata/ahci.h b/drivers/ata/ahci.h
index 3ca64c3d70..99c45f30fc 100644
--- a/drivers/ata/ahci.h
+++ b/drivers/ata/ahci.h
@@ -10,13 +10,15 @@
 #define AHCI_PCI_BAR		0x24
 #define AHCI_MAX_SG		56 /* hardware max is 64K */
 #define AHCI_CMD_SLOT_SZ	32
-#define AHCI_MAX_CMD_SLOT	32
+#define AHCI_MAX_CMDS		32
+#define AHCI_CMD_LIST_SZ	(AHCI_CMD_SLOT_SZ * AHCI_MAX_CMDS)
 #define AHCI_RX_FIS_SZ		256
 #define AHCI_CMD_TBL_HDR_SZ	0x80
 #define AHCI_CMD_TBL_CDB	0x40
-#define AHCI_CMD_TBL_SZ		AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 32)
-#define AHCI_PORT_PRIV_DMA_SZ	(AHCI_CMD_SLOT_SZ * AHCI_MAX_CMD_SLOT + \
-				AHCI_CMD_TBL_SZ	+ AHCI_RX_FIS_SZ)
+#define AHCI_CMD_TBL_ITM_SZ	16
+#define AHCI_CMD_TBL_SZ		(AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * AHCI_CMD_TBL_ITM_SZ))
+#define AHCI_PORT_PRIV_DMA_SZ	(AHCI_CMD_LIST_SZ + AHCI_CMD_TBL_SZ + AHCI_RX_FIS_SZ)
+
 #define AHCI_CMD_ATAPI		(1 << 5)
 #define AHCI_CMD_WRITE		(1 << 6)
 #define AHCI_CMD_PREFETCH	(1 << 7)
-- 
2.20.1