[PATCH v2 6/6] ARM: at91: sama5d3: add multiimage support for the microchip-ksz9477-evb

[Oleksij Rempel]

Am 23.04.21 um 17:29 schrieb Ahmad Fatoum:
> Hello Oleksij,
>
> On 23.04.21 16:28, Oleksij Rempel wrote:
>> -ENTRY_FUNCTION(start_sama5d3_xplained_ung8071, r0, r1, r2)
>> +SAMA5_ENTRY_FUNCTION(start_sama5d3_xplained_ung8071, r4)
>>  {
>>  	void *fdt;
>>
>> -	arm_cpu_lowlevel_init();
>> -
>>  	arm_setup_stack(SAMA5D3_SRAM_BASE + SAMA5D3_SRAM_SIZE);
>
> You should be able to drop this as well as the dbgu_init() after,
> because first stage already did it.

In case first stage was compile with same configs: yes.
In case first stage didn't prepared uart, the second stage will freeze
and first attempt to put any char.

>>
>>  	if (IS_ENABLED(CONFIG_DEBUG_LL))
>> diff --git a/arch/arm/mach-at91/include/mach/sama5d3-xplained-ddramc.h b/arch/arm/mach-at91/include/mach/sama5d3-xplained-ddramc.h
>> new file mode 100644
>> index 0000000000..6f829282c6
>> --- /dev/null
>> +++ b/arch/arm/mach-at91/include/mach/sama5d3-xplained-ddramc.h
>> @@ -0,0 +1,88 @@
>> +/* SPDX-License-Identifier: BSD-1-Clause
>> + *
>> + * Copyright (C) 2014, Atmel Corporation
>> + *
>> + * SAMA5D27 System-in-Package DDRAMC configuration
>> + */
>> +
>> +#include <mach/at91_ddrsdrc.h>
>> +#include <mach/ddramc.h>
>> +#include <mach/sama5d3_ll.h>
>> +
>> +static inline void sama5d3_xplained_ddrconf(void)
>> +{
>> +	const struct at91_ddramc_register conf = {
>> +		.mdr = AT91_DDRC2_DBW_32_BITS | AT91_DDRC2_MD_DDR2_SDRAM,
>> +
>> +		.cr = AT91_DDRC2_NC_DDR10_SDR9
>> +			| AT91_DDRC2_NR_13
>> +			| AT91_DDRC2_CAS_3
>> +			| AT91_DDRC2_DISABLE_RESET_DLL
>> +			| AT91_DDRC2_ENABLE_DLL
>> +			| AT91_DDRC2_ENRDM_ENABLE
>> +			| AT91_DDRC2_NB_BANKS_8
>> +			| AT91_DDRC2_NDQS_DISABLED
>> +			| AT91_DDRC2_DECOD_INTERLEAVED
>> +			| AT91_DDRC2_UNAL_SUPPORTED,
>> +
>> +		/*
>> +		 * The DDR2-SDRAM device requires a refresh every 15.625 us or 7.81 us.
>> +		 * With a 133 MHz frequency, the refresh timer count register must to be
>> +		 * set with (15.625 x 133 MHz) ~ 2084 i.e. 0x824
>> +		 * or (7.81 x 133 MHz) ~ 1039 i.e. 0x40F.
>> +		 */
>> +		.rtr = 0x40F,     /* Refresh timer: 7.812us */
>> +
>> +		/* One clock cycle @ 133 MHz = 7.5 ns */
>> +		.t0pr = AT91_DDRC2_TRAS_(6)	/* 6 * 7.5 = 45 ns */
>> +			| AT91_DDRC2_TRCD_(2)	/* 2 * 7.5 = 22.5 ns */
>> +			| AT91_DDRC2_TWR_(2)	/* 2 * 7.5 = 15   ns */
>> +			| AT91_DDRC2_TRC_(8)	/* 8 * 7.5 = 75   ns */
>> +			| AT91_DDRC2_TRP_(2)	/* 2 * 7.5 = 15   ns */
>> +			| AT91_DDRC2_TRRD_(2)	/* 2 * 7.5 = 15   ns */
>> +			| AT91_DDRC2_TWTR_(2)	/* 2 clock cycles min */
>> +			| AT91_DDRC2_TMRD_(2),	/* 2 clock cycles */
>> +
>> +		.t1pr = AT91_DDRC2_TXP_(2)		/* 2 clock cycles */
>> +			| AT91_DDRC2_TXSRD_(200)	/* 200 clock cycles */
>> +			| AT91_DDRC2_TXSNR_(19)	/* 19 * 7.5 = 142.5 ns */
>> +			| AT91_DDRC2_TRFC_(17),	/* 17 * 7.5 = 127.5 ns */
>> +
>> +		.t2pr = AT91_DDRC2_TFAW_(6)	/* 6 * 7.5 = 45 ns */
>> +			| AT91_DDRC2_TRTP_(2)		/* 2 clock cycles min */
>> +			| AT91_DDRC2_TRPA_(2)		/* 2 * 7.5 = 15 ns */
>> +			| AT91_DDRC2_TXARDS_(8)	/* = TXARD */
>> +			| AT91_DDRC2_TXARD_(8),	/* MR12 = 1 */
>> +	};
>> +	u32 reg;
>> +
>> +	/* enable ddr2 clock */
>> +	sama5d3_pmc_enable_periph_clock(SAMA5D3_ID_MPDDRC);
>> +	at91_pmc_enable_system_clock(IOMEM(SAMA5D3_BASE_PMC), AT91CAP9_PMC_DDR);
>> +
>> +
>> +	/* Init the special register for sama5d3x */
>> +	/* MPDDRC DLL Slave Offset Register: DDR2 configuration */
>> +	reg = AT91_MPDDRC_S0OFF_1
>> +		| AT91_MPDDRC_S2OFF_1
>> +		| AT91_MPDDRC_S3OFF_1;
>> +	writel(reg, SAMA5D3_BASE_MPDDRC + AT91_MPDDRC_DLL_SOR);
>> +
>> +	/* MPDDRC DLL Master Offset Register */
>> +	/* write master + clk90 offset */
>> +	reg = AT91_MPDDRC_MOFF_7
>> +		| AT91_MPDDRC_CLK90OFF_31
>> +		| AT91_MPDDRC_SELOFF_ENABLED | AT91_MPDDRC_KEY;
>> +	writel(reg, SAMA5D3_BASE_MPDDRC + AT91_MPDDRC_DLL_MOR);
>> +
>> +	/* MPDDRC I/O Calibration Register */
>> +	/* DDR2 RZQ = 50 Ohm */
>> +	/* TZQIO = 4 */
>> +	reg = AT91_MPDDRC_RDIV_DDR2_RZQ_50
>> +		| AT91_MPDDRC_TZQIO_4;
>> +	writel(reg, SAMA5D3_BASE_MPDDRC + AT91_MPDDRC_IO_CALIBR);
>> +
>> +	/* DDRAM2 Controller initialize */
>> +	at91_ddram_initialize(IOMEM(SAMA5D3_BASE_MPDDRC), IOMEM(SAMA5_DDRCS),
>> +			      &conf);
>> +}
>> diff --git a/images/Makefile.at91 b/images/Makefile.at91
>> index 00fa4cab27..7c32049270 100644
>> --- a/images/Makefile.at91
>> +++ b/images/Makefile.at91
>> @@ -14,6 +14,11 @@ pblb-$(CONFIG_MACH_MICROCHIP_KSZ9477_EVB) += start_sama5d3_xplained_ung8071
>>  FILE_barebox-microchip-ksz9477-evb.img = start_sama5d3_xplained_ung8071.pblb
>>  image-$(CONFIG_MACH_MICROCHIP_KSZ9477_EVB) += barebox-microchip-ksz9477-evb.img
>>
>> +pblb-$(CONFIG_MACH_MICROCHIP_KSZ9477_EVB) += start_sama5d3_xplained_ung8071_xload_mmc
>> +MAX_PBL_IMAGE_SIZE_start_sama5d3_xplained_ung8071_xload_mmc = 0xffff
>> +FILE_barebox-microchip-ksz9477-evb-xload-mmc.img = start_sama5d3_xplained_ung8071_xload_mmc.pblb
>> +image-$(CONFIG_MACH_MICROCHIP_KSZ9477_EVB) += barebox-microchip-ksz9477-evb-xload-mmc.img
>> +
>>  pblb-$(CONFIG_MACH_SAMA5D27_SOM1) += start_sama5d27_som1_ek
>>  FILE_barebox-sama5d27-som1-ek.img = start_sama5d27_som1_ek.pblb
>>  image-$(CONFIG_MACH_SAMA5D27_SOM1) += barebox-sama5d27-som1-ek.img
>>
>


--
Regards,
Oleksij