reset / watchdog on an imx7d soc

[Fabio Estevam]

Hi Giorgio,

On Mon, Jun 29, 2020 at 1:33 PM Giorgio Dal Molin
<giorgio.nicole at arcor.de> wrote:

> U-Boot configures the ddr3 with c code in its board code 'lowlevel.c'.
> Looking at the code I noticed this special treatment:
>
> static void spl_dram_init(void)
> {
> ...
>         /*
>          * Make sure that both aresetn/core_ddrc_rstn and preset/PHY reset
>          * bits are set after WDOG reset event. DDRC_PRST can only be
>          * released when DDRC clock inputs are stable for at least 30 cycles.
>          */
>         writel(SRC_DDRC_RCR_DDRC_CORE_RST_MASK | SRC_DDRC_RCR_DDRC_PRST_MASK, &src_regs->ddrc_rcr);
>         udelay(500);
> ...
>
> This writel() set both reset bits, the DDRC_CORE (0x2) and the DDRC_PRST (0x1) of the SRC
> register 0x30391000.
> Unfortunately, if I try also to set both bits in my DCD table then barebox doesn't boot anymore;
> I also tried to port the uboot spl_dram_init(void) to my barebox lowlevel.c and I could eventually
> boot barebox with an empty DCD but still adding the second bit (SRC_DDRC_RCR_DDRC_PRST_MASK)
> hangs the soc.

Does it help if you try to apply this U-Boot commit to Barebox?
https://gitlab.denx.de/u-boot/u-boot/-/commit/0e06d63d195670f5181958f43216d7106c05357f