[PATCH 04/12] arm: cpu: add arm64 specific code

[Sascha Hauer]

On Thu, Jun 02, 2016 at 10:06:50AM +0200, Raphael Poggi wrote:
> This patch adds arm64 specific codes, which are:
> 	- exception support
> 	- cache support
> 	- rework Makefile to support arm64
> 
> Signed-off-by: Raphael Poggi <poggi.raph at gmail.com>
> ---
>  arch/arm/cpu/Makefile        |  17 ++++-
>  arch/arm/cpu/cache-armv8.S   | 168 +++++++++++++++++++++++++++++++++++++++++++
>  arch/arm/cpu/cache.c         |  19 +++++
>  arch/arm/cpu/exceptions_64.S | 127 ++++++++++++++++++++++++++++++++
>  arch/arm/cpu/interrupts.c    |  47 ++++++++++++
>  arch/arm/cpu/lowlevel.S      |  38 ++++++++++
>  arch/arm/include/asm/cache.h |   9 +++
>  7 files changed, 423 insertions(+), 2 deletions(-)
>  create mode 100644 arch/arm/cpu/cache-armv8.S
>  create mode 100644 arch/arm/cpu/exceptions_64.S
> 
> --- a/arch/arm/cpu/lowlevel.S
> +++ b/arch/arm/cpu/lowlevel.S
> @@ -3,6 +3,7 @@
>  #include <asm/system.h>
>  
>  .section ".text_bare_init_","ax"
> +#if __LINUX_ARM_ARCH__ <= 7
>  ENTRY(arm_cpu_lowlevel_init)
>  	/* set the cpu to SVC32 mode, mask irq and fiq */
>  	mrs	r12, cpsr
> @@ -56,3 +57,40 @@ ENTRY(arm_cpu_lowlevel_init)
>  
>  	mov	pc, lr
>  ENDPROC(arm_cpu_lowlevel_init)
> +#else
> +ENTRY(arm_cpu_lowlevel_init)
> +	adr	x0, vectors
> +	mrs	x1, CurrentEL
> +	cmp	x1, #0xC		/* Check EL3 state */
> +	b.eq	1f
> +	cmp	x1, #0x8		/* Check EL2 state */
> +	b.eq	2f
> +	cmp	x1, #0x4		/* Check EL1 state */
> +	b.eq	3f
> +
> +1:
> +	msr	vbar_el3, x0
> +	mov	x0, #1			/* Non-Secure EL0/1 */
> +	orr	x0, x0, #(1 << 10)	/* 64-bit EL2 */
> +	msr	scr_el3, x0
> +	msr	cptr_el3, xzr
> +	b	done
> +
> +2:
> +	msr	vbar_el2, x0
> +	mov	x0, #0x33ff		/* Enable FP/SIMD */
> +	msr	cptr_el2, x0
> +	b	done
> +
> +
> +3:
> +	msr	vbar_el1, x0
> +	mov	x0, #(3 << 20)		/* Enable FP/SIMD */
> +	msr	cpacr_el1, x0
> +	b	done
> +
> +done:
> +	ret
> +
> +ENDPROC(arm_cpu_lowlevel_init)
> +#endif

Better create a lowlevel64.S? The code is completely different anyway.

Sascha

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