[PATCH 2/4] MIPS: avoid excessive exception

[Antony Pavlov]

This commit clears ERL (ERror Level) flag on start.
If this flag is set then we get 'TLB miss on load or ifetch'
just after return from exception.

Signed-off-by: Antony Pavlov <antonynpavlov at gmail.com>
---
 arch/mips/include/asm/pbl_macros.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/mips/include/asm/pbl_macros.h b/arch/mips/include/asm/pbl_macros.h
index 681b40a..c4ae6a2 100644
--- a/arch/mips/include/asm/pbl_macros.h
+++ b/arch/mips/include/asm/pbl_macros.h
@@ -145,7 +145,7 @@ copy_loop_exit:
 	.set	push
 	.set	noreorder
 	mfc0	k0, CP0_STATUS
-	li	k1, ~ST0_IE
+	li	k1, ~(ST0_ERL | ST0_IE)
 	and	k0, k1
 	mtc0	k0, CP0_STATUS
 	.set	pop
-- 
2.6.2