[PATCH v2 08/25] clk: tegra30: register i2c clocks
Lucas Stach
dev at lynxeye.de
Wed May 14 13:45:35 PDT 2014
Signed-off-by: Lucas Stach <dev at lynxeye.de>
---
arch/arm/mach-tegra/include/mach/tegra30-car.h | 2 ++
drivers/clk/tegra/clk-tegra30.c | 16 ++++++++++++++++
2 files changed, 18 insertions(+)
diff --git a/arch/arm/mach-tegra/include/mach/tegra30-car.h b/arch/arm/mach-tegra/include/mach/tegra30-car.h
index ce110602fca3..286a2a613a8d 100644
--- a/arch/arm/mach-tegra/include/mach/tegra30-car.h
+++ b/arch/arm/mach-tegra/include/mach/tegra30-car.h
@@ -25,6 +25,8 @@
#define CRC_CLK_SOURCE_MSEL_SRC_PLLM 2
#define CRC_CLK_SOURCE_MSEL_SRC_CLKM 3
+#define CRC_CLK_SOURCE_I2C4 0x3c4
+
#define CRC_RST_DEV_V_SET 0x430
#define CRC_RST_DEV_V_MSELECT (1 << 3)
diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index 9536288f89ac..3b508304c5d7 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -296,6 +296,22 @@ static void tegra30_periph_init(void)
clks[TEGRA30_CLK_SDMMC4] = tegra_clk_register_periph("sdmmc4",
mux_pllpcm_clkm, ARRAY_SIZE(mux_pllpcm_clkm), car_base,
CRC_CLK_SOURCE_SDMMC4, TEGRA30_CLK_SDMMC4, 1);
+
+ clks[TEGRA30_CLK_I2C1] = tegra_clk_register_periph_div16("i2c1",
+ mux_pllpcm_clkm, ARRAY_SIZE(mux_pllpcm_clkm), car_base,
+ CRC_CLK_SOURCE_I2C1, TEGRA30_CLK_I2C1, 1);
+ clks[TEGRA30_CLK_I2C2] = tegra_clk_register_periph_div16("i2c2",
+ mux_pllpcm_clkm, ARRAY_SIZE(mux_pllpcm_clkm), car_base,
+ CRC_CLK_SOURCE_I2C2, TEGRA30_CLK_I2C2, 1);
+ clks[TEGRA30_CLK_I2C3] = tegra_clk_register_periph_div16("i2c3",
+ mux_pllpcm_clkm, ARRAY_SIZE(mux_pllpcm_clkm), car_base,
+ CRC_CLK_SOURCE_I2C3, TEGRA30_CLK_I2C3, 1);
+ clks[TEGRA30_CLK_I2C4] = tegra_clk_register_periph_div16("i2c4",
+ mux_pllpcm_clkm, ARRAY_SIZE(mux_pllpcm_clkm), car_base,
+ CRC_CLK_SOURCE_I2C4, TEGRA30_CLK_I2C4, 1);
+ clks[TEGRA30_CLK_I2C5] = tegra_clk_register_periph_div16("i2c5",
+ mux_pllpcm_clkm, ARRAY_SIZE(mux_pllpcm_clkm), car_base,
+ CRC_CLK_SOURCE_DVC, TEGRA30_CLK_I2C5, 1);
}
static struct tegra_clk_init_table init_table[] = {
--
1.9.0
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