[PATCH 1/6] ARM: i.MX6Q: Fix IOMUXC GPR1 bit 21 (ENET_CLK_SEL)

[Sascha Hauer]

From: Philipp Zabel <p.zabel at pengutronix.de>

This bit selects whether the ENET_REF_CLK is sourced from the internal
ENET PLL (ANATOP), or from an external clock source connected to the
GPIO_16 pad.

Signed-off-by: Philipp Zabel <p.zabel at pengutronix.de>
---
 include/mfd/imx6q-iomuxc-gpr.h | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/include/mfd/imx6q-iomuxc-gpr.h b/include/mfd/imx6q-iomuxc-gpr.h
index db43d59..53efc63 100644
--- a/include/mfd/imx6q-iomuxc-gpr.h
+++ b/include/mfd/imx6q-iomuxc-gpr.h
@@ -103,9 +103,9 @@
 #define IMX6Q_GPR1_EXC_MON_MASK			BIT(22)
 #define IMX6Q_GPR1_EXC_MON_OKAY			0x0
 #define IMX6Q_GPR1_EXC_MON_SLVE			BIT(22)
-#define IMX6Q_GPR1_MIPI_IPU2_SEL_MASK		BIT(21)
-#define IMX6Q_GPR1_MIPI_IPU2_SEL_GASKET		0x0
-#define IMX6Q_GPR1_MIPI_IPU2_SEL_IOMUX		BIT(21)
+#define IMX6Q_GPR1_ENET_CLK_SEL_MASK		BIT(21)
+#define IMX6Q_GPR1_ENET_CLK_SEL_PAD		0
+#define IMX6Q_GPR1_ENET_CLK_SEL_ANATOP		BIT(21)
 #define IMX6Q_GPR1_MIPI_IPU1_MUX_MASK		BIT(20)
 #define IMX6Q_GPR1_MIPI_IPU1_MUX_GASKET		0x0
 #define IMX6Q_GPR1_MIPI_IPU1_MUX_IOMUX		BIT(20)
-- 
1.9.0