[PATCH 5/6] CPUIMX51: configure SD1 iomux when ESDHC is enabled

[Eric Bénard]

Signed-off-by: Eric Bénard <eric at eukrea.com>
---
 arch/arm/boards/eukrea_cpuimx51/eukrea_cpuimx51.c |    9 +++++++++
 1 files changed, 9 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boards/eukrea_cpuimx51/eukrea_cpuimx51.c b/arch/arm/boards/eukrea_cpuimx51/eukrea_cpuimx51.c
index a128d50..a2db6d9 100644
--- a/arch/arm/boards/eukrea_cpuimx51/eukrea_cpuimx51.c
+++ b/arch/arm/boards/eukrea_cpuimx51/eukrea_cpuimx51.c
@@ -88,6 +88,15 @@ static struct pad_desc eukrea_cpuimx51_pads[] = {
 	MX51_PAD_NANDF_CS1__NANDF_CS1,
 	/* LCD BL */
 	MX51_PAD_DI1_D1_CS__GPIO3_4,
+#ifdef CONFIG_MCI_IMX_ESDHC
+	/* SD 1 */
+	MX51_PAD_SD1_CMD__SD1_CMD,
+	MX51_PAD_SD1_CLK__SD1_CLK,
+	MX51_PAD_SD1_DATA0__SD1_DATA0,
+	MX51_PAD_SD1_DATA1__SD1_DATA1,
+	MX51_PAD_SD1_DATA2__SD1_DATA2,
+	MX51_PAD_SD1_DATA3__SD1_DATA3,
+#endif
 };
 
 #define GPIO_LAN8700_RESET	(1 * 32 + 31)
-- 
1.7.6.4