[PATCH 3/6] CPUIMX51: add ARM errata and enable L2 cache

[Eric Bénard]

- add ARM errata ID #468414
- enable L2 cache to get better performances

Signed-off-by: Eric Bénard <eric at eukrea.com>
---
 arch/arm/boards/eukrea_cpuimx51/lowlevel_init.S |   10 ++++++++++
 1 files changed, 10 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boards/eukrea_cpuimx51/lowlevel_init.S b/arch/arm/boards/eukrea_cpuimx51/lowlevel_init.S
index 0b3726f..ee3b0fc 100644
--- a/arch/arm/boards/eukrea_cpuimx51/lowlevel_init.S
+++ b/arch/arm/boards/eukrea_cpuimx51/lowlevel_init.S
@@ -57,6 +57,11 @@
 board_init_lowlevel:
 	mov     r10, lr
 
+	/* ARM errata ID #468414 */
+	mrc 15, 0, r1, c1, c0, 1
+	orr r1, r1, #(1 << 5)    /* enable L1NEON bit */
+	mcr 15, 0, r1, c1, c0, 1
+
 	/* explicitly disable L2 cache */
 	mrc 15, 0, r0, c1, c0, 1
 	bic r0, r0, #0x2
@@ -76,6 +81,11 @@ board_init_lowlevel:
 
 	mcr 15, 1, r0, c9, c0, 2
 
+	/* enable L2 cache */
+	mrc 15, 0, r0, c1, c0, 1
+	orr r0, r0, #2
+	mcr 15, 0, r0, c1, c0, 1
+
 	ldr r0, =MX51_CCM_BASE_ADDR
 
 	/* Gate of clocks to the peripherals first */
-- 
1.7.6.4