[PATCH 6/6] qoriq: add support for WatchGuard Firebox M300

[Stijn Tintel]

On 22/08/2021 03:06, Alberto Bursi wrote:
>
>
> On 22/08/21 01:15, Stijn Tintel wrote:
>> This device is based on NXP's QorIQ T2081QDS board, with a quad-core
>> dual-threaded 1.5 GHz ppc64 CPU and 4GB ECC RAM. The board has 5
>
> A few questions about this device hardware:
> is there anything in uboot or Linux that shows or even hints at the
> fact that ECC is working or enabled? I have also read the official
> docs from Watchguard and they say that it is using ECC ram but I'm
> always skeptical because that can also just mean they use a ECC DIMM
> in non-ECC mode. PC motherboard manufacturers lied many times in the
> past about this so I'm curious if there is something more.
On the M300, U-Boot shows ECC is on:

DRAM:  Initializing....using SPD
Detected UDIMM TS512MLK72W6H
4 GiB (DDR3, 64-bit, CL=11, ECC on)

On Linux, it believe it is enabled as well, as the fsl_ddr_edac driver
seems to register without errors:

[    2.697625] Freescale(R) MPC85xx EDAC driver, (C) 2006 Montavista
Software
[    2.705303] EDAC MC0: Giving out device to module fsl_ddr_edac
controller fsl_mc_err: DEV fsl_mc_err (INTERRUPT)
[    2.715548] fsl_ddr_edac acquired irq 490 for MC
[    2.720173] fsl_ddr_edac MC err registered

>
> Also, both this and the M200 (the "cheaper" version with a T1042 CPU
> instead) seem to have socketed DIMM RAM, is it a custom thing with
> hardcoded mem size or can it be replaced with a different DIMM module?
> Would also be cool if M200 could support ECC RAM but that's something
> you probably don't know much about.

The M200 comes with a 2GB non-ECC DDR3L module. Putting the 4GB ECC
module of the M300 in the M200 shows that in U-Boot, ECC is also enabled:

DRAM:  Initializing....using SPD
Detected UDIMM TS512MLK72W6H
Not enough bank(chip-select) for CS0+CS1 on controller 0, interleaving
disabled!
4 GiB (DDR3, 64-bit, CL=11, ECC on)

On Linux, it seems to show the same as on the M300:

[    3.214732] Freescale(R) MPC85xx EDAC driver, (C) 2006 Montavista
Software
[    3.222542] EDAC MC0: Giving out device to module fsl_ddr_edac
controller fsl_mc_err: DEV fsl_mc_err (INTERRUPT)
[    3.232812] fsl_ddr_edac acquired irq 490 for MC
[    3.237436] fsl_ddr_edac MC err registered

And I see > 2GB:

root at OpenWrt:/# free -m
              total        used        free      shared  buff/cache  
available
Mem:        3989420       74780     3877808          84       36832    
3863916
Swap:             0           0           0

Putting the only other DDR3L module I have available in either device
didn't work:

DRAM:  Initializing....using SPD
Detected RDIMM HMT31GR7CFR4A-H9
DDR clock (MCLK cycle 1250 ps) is faster than the slowest DIMM(s)
(tCKmin 1500 ps) can support.
The choosen cas latency 27 is too large
Error: unsupported cas latency for mode register
Waiting for D_INIT timeout. Memory may not work.

Carefully selected other modules might work, and maybe it's even
possible to get this one to work, by modifying some values in the RCW.
This will require some more research.

At least you know that the 4GB ECC module used in the M300 will work
fine in the M200.

>
> Do you think adding the Watchguard M200 would be mostly a copy-paste
> job? from what I have seen online it should be more or less the same
> board but with a lower end CPU.
> I might get one in the near future to do this myself if it's the case.

The T1042 CPU in the M200 is e5500, as opposed to the e6500 in the M300.
As Rui already explained, the T1042 does not support AltiVec, which musl
expects for all PPC64 CPUs. I was able to boot Linux on it after
patching the vector instructions out of the musl PPC64 assembly code
[1], but I suspect I also got bitten by the THREAD_SHIFT value being set
to the default for PPC32. I have just verified that with THREAD_SHIFT
correctly set and that musl hack, the M200 also boots fine, to be able
to give you the data about different RAM modules and ECC. The m200
branch in my staging tree [2] should be a good starting point for people
who want to continue on it. Once the qoriq target made it in the tree,
I'll have another go at the M200, and I'll move it to the qoriq target
then (it's still in the mpc85xx target atm), and do the DTS like I did
for the M300.

Stijn

[1]
https://git.openwrt.org/?p=openwrt/staging/stintel.git;a=blob;f=toolchain/musl/patches/999-musl-drop-vx-insns.patch;h=9f3fdd03ead542351990009d3841daa036932695;hb=3537add5f0d67f4c6cc49d09d1dd2b8305a2e7dc
[2]
https://git.openwrt.org/?p=openwrt/staging/stintel.git;a=shortlog;h=refs/heads/m200