[PATCH] platform: generic: allwinner: correct mhpmevent count

[Guo Ren]

On Sun, Aug 6, 2023 at 1:04 AM Anup Patel <anup at brainfault.org> wrote:
>
> On Thu, Aug 3, 2023 at 7:20 AM Inochi Amaoto <inochiama at outlook.com> wrote:
> >
> > Only the CSR mhpmevent 3-9,13-17 of D1 have valid function, so reduce
> > the mhpm_count to 15 to avoid invalid usage.
> >
> > Signed-off-by: Inochi Amaoto <inochiama at outlook.com>
> > ---
> >  platform/generic/allwinner/sun20i-d1.c | 3 ++-
> >  1 file changed, 2 insertions(+), 1 deletion(-)
> >
> > diff --git a/platform/generic/allwinner/sun20i-d1.c b/platform/generic/allwinner/sun20i-d1.c
> > index 0f0a9f3..94a3a5e 100644
> > --- a/platform/generic/allwinner/sun20i-d1.c
> > +++ b/platform/generic/allwinner/sun20i-d1.c
> > @@ -272,7 +272,8 @@ static int sun20i_d1_extensions_init(const struct fdt_match *match,
> >         sbi_pmu_set_device(&thead_c9xx_pmu_device);
> >
> >         /* auto-detection doesn't work on t-head c9xx cores */
> > -       hfeatures->mhpm_count = 29;
> > +       /* D1 has 29 mhpmevent csrs, but only 3-9,13-17 have valid value */
> > +       hfeatures->mhpm_count = 15;
>
> With the latest non-contiguous counter support, we need to set
> mhpm_mask as well.
> I have taken care of this at the time of merging this patch.
>
> Reviewed-by: Anup Patel <anup at brainfault.org>
>
> Applied this patch to the riscv/opensbi repo.
Sorry for the delayed reply. I think we need more tests on this patch.
Now my colleagues are cooperating with Inochi to solve the problem.

We are also solving the perf record problem on D1, so I'm unsure about
the final solution. I recommend you hold this patch for a while. Maybe
we would adjust it.

ps:
Include Heiko email

>
> Thanks,
> Anup
>
> >         hfeatures->mhpm_bits = 64;
> >
> >         return 0;
> > --
> > 2.41.0
> >
> >
> > --
> > opensbi mailing list
> > opensbi at lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/opensbi



-- 
Best Regards
 Guo Ren