[PATCH] platform: generic: allwinner: correct mhpmevent count

[Anup Patel]

On Thu, Aug 3, 2023 at 7:20 AM Inochi Amaoto <inochiama at outlook.com> wrote:
>
> Only the CSR mhpmevent 3-9,13-17 of D1 have valid function, so reduce
> the mhpm_count to 15 to avoid invalid usage.
>
> Signed-off-by: Inochi Amaoto <inochiama at outlook.com>
> ---
>  platform/generic/allwinner/sun20i-d1.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/platform/generic/allwinner/sun20i-d1.c b/platform/generic/allwinner/sun20i-d1.c
> index 0f0a9f3..94a3a5e 100644
> --- a/platform/generic/allwinner/sun20i-d1.c
> +++ b/platform/generic/allwinner/sun20i-d1.c
> @@ -272,7 +272,8 @@ static int sun20i_d1_extensions_init(const struct fdt_match *match,
>         sbi_pmu_set_device(&thead_c9xx_pmu_device);
>
>         /* auto-detection doesn't work on t-head c9xx cores */
> -       hfeatures->mhpm_count = 29;
> +       /* D1 has 29 mhpmevent csrs, but only 3-9,13-17 have valid value */
> +       hfeatures->mhpm_count = 15;

With the latest non-contiguous counter support, we need to set
mhpm_mask as well.
I have taken care of this at the time of merging this patch.

Reviewed-by: Anup Patel <anup at brainfault.org>

Applied this patch to the riscv/opensbi repo.

Thanks,
Anup

>         hfeatures->mhpm_bits = 64;
>
>         return 0;
> --
> 2.41.0
>
>
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