[PATCH v2 1/1] arm64: dts: rockchip: rk3528: Add CPU frequency scaling support

[Alexey Charkov]

On Thu, Jul 17, 2025 at 11:01 AM Chukun Pan <amadeus at jmu.edu.cn> wrote:
>
> Hi Jonas,
>
> > One possible difference here is that the actual CPU rate is controlled
> > by a PVTPLL where TF-A will configure a osc ring-length based on the
> > requested rate and Linux only configure the regulator voltage.
> >
> > I have no idea if the configuration made by TF-A will have any affect on
> > power usage, but I suggest we keep all opp here because both TF-A and
> > Linux is involved in configuring the CPU rate.
> >
> > The measured rate can typically be read from a PVTPLL status reg, it
> > will be different depending on the ring-length, voltage and silicon
> > quality for the rates >= 816 MHz.
>
> Alexey suggested that we remove 408MHz, 600MHz and 816MHz from the
> opp-table. Do you think it is acceptable to use 850mV for 1008MHz?

But why 850 mV? Vendor .dtsi [1] implies that chips with leakage
values of L0..L4 might be unstable at this frequency with a 850 mV
supply and need 875 mV instead.

As long as we don't read out OTP leakage values, we should pick a
voltage for each OPP that is sufficient for all possible chip
characteristics, meaning the maximum of all opp-microvolt* given in
each OPP. This will result in higher -L* chips burning more power than
they have to, but at least they will be stable.

[1] https://github.com/rockchip-linux/kernel/blob/792a7d4273a59e80dafca48ba11438f43a6d8bda/arch/arm64/boot/dts/rockchip/rk3528.dtsi#L268

Best regards,
Alexey