[PATCH 2/2] PCI: dw-rockchip: Change get_lttssm() to provide L1ss info

[Bjorn Helgaas]

On Tue, Nov 25, 2025 at 09:53:52AM +0800, Shawn Lin wrote:
> This patch renames rockchip_pcie_get_ltssm() to rockchip_pcie_get_ltssm_reg()
> and adds rockchip_pcie_get_ltssm() to get_lttssm() callback to in order to
> show the proper L1 substates. The PCIE_CLIENT_LTSSM_STATUS[5:0] register returns
> the same ltssm layout as enum dw_pcie_ltssm. So we only need to tell L1ss apart
> and return the proper value defined in pcie-designware.h.
> 
> cat /sys/kernel/debug/dwc_pcie_a40000000.pcie/ltssm_status
> L1_2 (0x142)

s/get_lttssm/get_ltssm/ (subject and commit log)
s/This patch renames/Rename/ (imperative mood)
s/and adds/and add/ (imperative mood)
s/ltssm/LTSSM/
s/L1ss/L1 PM Substates/

Wrap the commit log to fit in 75 columns to allow for "git log"
indenting everything.

Indent the "cat /sys/..." example two spaces.

> +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
> +static enum dw_pcie_ltssm rockchip_pcie_get_ltssm(struct dw_pcie *pci)
> +{
> +	struct rockchip_pcie *rockchip = to_rockchip_pcie(pci);
> +	u32 val = rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_CDM_RASDES_TBA_INFO_CMN);
> +

Wrap to fit in 80 columns like the rest of the file.  Or possibly
reduce the length of "PCIE_CLIENT_CDM_RASDES_TBA_INFO_CMN", which
might be excessively descriptive.

> +	if (val & PCIE_CLIENT_CDM_RASDES_TBA_L1_1)
> +		return DW_PCIE_LTSSM_L1_1;
> +	else if (val & PCIE_CLIENT_CDM_RASDES_TBA_L1_2)
> +		return DW_PCIE_LTSSM_L1_2;
> +	else
> +		return rockchip_pcie_get_ltssm_reg(rockchip) &
> +			PCIE_LTSSM_STATUS_MASK;

None of these "else" uses are needed:

  if (val & PCIE_CLIENT_CDM_RASDES_TBA_L1_1)
    return DW_PCIE_LTSSM_L1_1;

  if (val & PCIE_CLIENT_CDM_RASDES_TBA_L1_2)
    return DW_PCIE_LTSSM_L1_2;

  return rockchip_pcie_get_ltssm_reg(rockchip) & PCIE_LTSSM_STATUS_MASK;