[RESEND PATCH v3] arm64: dts: rockchip: Add PCIe clkreq stuff for RK3588 EVB1

[Anand Moon]

Hi Shawn,

On Mon, 8 Dec 2025 at 05:55, Shawn Lin <shawn.lin at rock-chips.com> wrote:
>
> 在 2025/12/07 星期日 15:50, Anand Moon 写道:
> > Hi Shawn,
> >
> > On Thu, 4 Dec 2025 at 06:21, Shawn Lin <shawn.lin at rock-chips.com> wrote:
> >>
> >> Add supports-clkreq and pinmux for PCIe ASPM L1 substates.
> >>
> >> Signed-off-by: Shawn Lin <shawn.lin at rock-chips.com>
> >> Acked-by: Manivannan Sadhasivam <mani at kernel.org>
> >> Reviewed-by: Hans Zhang <hans.zhang at cixtech.com>
> >> ---
> > Thanks, are there plans to support this feature on the remaining
> > RK356x and RK3588 SBCs?
>
> It needs to be checked on a per-board basis.
>
According to the schematics, all Rockchip PCIe interfaces include the
CLKREQ# and WAKE# GPIO pins.

[1] https://dl.radxa.com/rock5/5b+/docs/hw/radxa_rock5bp_v1.2_schematic.pdf
[2] https://wiki.odroid.com/_media/odroid-m1/hardware/m1_main_rev1.0.pdf
[3] https://wiki.odroid.com/_media/odroid-m2/hardware/m2_main_rev1.0_240611.pdf

> We're happy for folks to add it themselves for their boards once they've
> verified the clkreqpin on their hardware.

The commit 4294e3211178 (“arm64: dts: rockchip: Split up RK3588’s PCIe
pinctrls”)
separates the CLKREQ#, PERST#, and WAKE# pinctrl signals for the
RK3588 platform.
Should we apply a similar split for the RK356x pinctrl definitions as well?

Thanks
-Anand