Increasing priority of a DMAC1 hardware request ID on RK3568?

[Pavel Hofman]

Dne 06. 09. 23 v 10:42 Pavel Hofman napsal(a):
> Please is it possible to increase a priority of a DMAC1 hardware request 
> (I2S1_8ch_tx specifically) on RK3568? I could not find any DMAC priority 
> mentioned in the RK3568 TRMs.
> 

The PL330 DMAC documentation specifically mentions that no priority of 
channels can be set.

But the DMAC0/1 clock on RK3568 "acl_bus" has multiple parents 
("gpll_200m", "gpll_150m", "gpll_100m", "xin24m") which corresponds to 
the documentation - CRU selector CRU_CLKSEL_CON49 aclk_bus_sel/aclk_bus 
clock mux.

The default value of that selector is 200MHz, yet my RK3568 has acl_bus 
clock switched to parent gpll_150m, i.e. only 150MHz. Perhaps keeping 
the default 200MHz would increase the DMAC performance?

Unfortunately I could not find where this particular clock gets switched 
to the non-default parent in the kernel code. Other clocks using the 
same parents gpll200_gpll150_gpll100_xin24m_p (e.g. aclk_gic_audio) do 
run at the default gpll_200m.

Additionally, the datasheet mentions bits aclk_en ("enable aclk_bus 
switch to lower frequency") and switch_en ("enable aclk_bus/pclk_bus 
automatically switched to lower frequency when pdbus is inactive") in 
register CRU_AUTOCS_BUS_CON1. By default they both should be disabled. I 
could not find any explanation of their effect in the datasheet, kernel 
does not seem to touch that register at all, as far as I could search.

Please can someone knowledgable of the Rockchip clocking help with 
locating the reason the acl_bus runs only at the non-default 150MHz?

Thanks a lot in advance.

Pavel.