Increasing priority of a DMAC1 hardware request ID on RK3568?

[Pavel Hofman]

Hi,

Please is it possible to increase a priority of a DMAC1 hardware request 
(I2S1_8ch_tx specifically) on RK3568? I could not find any DMAC priority 
mentioned in the RK3568 TRMs.

Google finds some information about AHB Arbiter Matrix which the RK3568 
TRMs do not mention.

I am getting FIFO issues for I2S1 running at 768kHz samplerate. 
Increasing dma.maxburst from 8 to the max 16 in the I2S driver 
(rockchip_i2s_tdm_c) helped notably, but still FIFO failures occur, 
about 10 per second. In some test runs the DMA transfers managed OK for 
like half a second every 3 seconds, but I do not know how to monitor 
other transfers to find the possible colliding traffic.

Cpufreq scaling governors for all cores are on "performance".

Increasing priority of these specific DMA transfers would seem like a 
possible way to improvement, if that is technically possible.

Knowing for sure that changing the priority of those transfers is not 
possible would be also very useful as I would know some different SoC 
has to be used instead.

Thank you very much for an advice and hints.

With regards,

Pavel.