[PATCH 2/3] mtd: spi-nor: Bindings for Rockchip serial flash controller

[Chris Morgan]

From: Chris Morgan <macromorgan at hotmail.com>

Add binding document for the Rockchip serial flash controller.

Signed-off-by: Chris Morgan <macromorgan at hotmail.com>
---
 .../mtd/rockchip,serialflash-controller.yaml  | 100 ++++++++++++++++++
 1 file changed, 100 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/mtd/rockchip,serialflash-controller.yaml

diff --git a/Documentation/devicetree/bindings/mtd/rockchip,serialflash-controller.yaml b/Documentation/devicetree/bindings/mtd/rockchip,serialflash-controller.yaml
new file mode 100644
index 000000000000..97ea89fde3fb
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/rockchip,serialflash-controller.yaml
@@ -0,0 +1,100 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mtd/rockchip,serialflash-controller.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip SoCs Serial FLASH Controller (SFC)
+
+maintainers:
+  - Andy Yan <andy.yan at rock-chips.com>
+
+properties:
+  compatible:
+    oneOf:
+      - const: rockchip,px30-sfc
+      - const: rockchip,rv1108-sfc
+      - items:
+        - const: rockchip,sfc
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    minItems: 2
+    items:
+      - description: Module Clock
+      - description: Bus Clock
+
+  clock-names:
+    minItems: 2
+    items:
+      - const: sfc
+      - const: hsfc
+
+  power-domains:
+    maxItems: 1
+
+  rockchip,sfc-no-dma:
+    - descrption: Boolean value for disabling DMA
+
+patternProperties:
+  "^spi-nor@[0-3]$":
+    type: object
+    properties:
+      reg:
+        minimum: 0
+        maximum: 3
+
+      spi-max-frequency:
+        maxItems: 1
+	  - description: Maximum frequency for SPI Flash
+
+      compatible:
+        oneOf:
+          - const: jedec,spi-nor
+
+      spi-rx-bus-width:
+        maxItems: 1
+          - description: RX Bus Width (1x, 2x, or 4x mode)
+
+
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+  - clock-names
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/px30-cru.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+sfc: spi at ff3a0000 {
+	compatible = "rockchip,px30-sfc","rockchip,sfc";
+	#address-cells = <1>;
+	#size-cells = <0>;
+	reg = <0x0 0xff3a0000 0x0 0x4000>;
+	interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+	clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
+	clock-names = "sfc", "hsfc";
+	pinctrl-names = "default";
+	pinctrl-0 = <&sfc_clk &sfc_cs &sfc_bus2>;
+	power-domains = <&power PX30_PD_MMC_NAND>;
+
+	nor_flash: spi-nor at 0 {
+		reg = <0>;
+		compatible = "xtx,xt25f128b","jedec,spi-nor";
+		spi-rx-bus-width = <2>;
+		spi-max-frequency = <108000000>;
+	};
+};
+
+...
-- 
2.25.1