[PATCH 13/18] riscv: dts: zhihe: add A210 core support

[Conor Dooley]

On Thu, Oct 22, 2026 at 03:53:33AM +0800, Han Gao via B4 Relay wrote:
> +	soc {
> +		compatible = "simple-bus";
> +		ranges;
> +		#address-cells = <2>;
> +		dma-noncoherent;
> +		#size-cells = <2>;
> +
> +		clk: clock-controller at 260000 {
> +			compatible = "zhihe,a210-clk";
> +			reg = <0x0 0x00260000 0x0 0x1000>,
> +			      <0x0 0x00250000 0x0 0x1000>,
> +			      <0x0 0x10141600 0x0 0x100>,
> +			      <0x0 0x10141400 0x0 0x100>,
> +			      <0x0 0x04810000 0x0 0x1000>,
> +			      <0x0 0x05810000 0x0 0x1000>,
> +			      <0x0 0x04900000 0x0 0x1000>,
> +			      <0x0 0x20250000 0x0 0x1000>,
> +			      <0x0 0x10140000 0x0 0xe00>;

This looks very much like an incorrect modelling of the device.
Most of these should be individual devices, and those labeled "sysreg"
probably should be syscons as they likely contain multiple functions,
not just clocks?

> +			reg-names = "pll-wrap", "top-crg", "cpu-ss-clk-sysreg",
> +				    "cpu-ss-cpu-pll", "ddr0-sysreg",
> +				    "ddr1-sysreg", "slc-dual-sysreg",
> +				    "top-crg-t", "cpu-ss-ccu";
> +			#clock-cells = <1>;
> +			clocks = <&osc_32k>, <&osc_24m>, <&rc_24m>;
> +			clock-names = "osc-32k", "osc-24m", "rc-24m";
> +		};
> +
> +		clk_peri: clock-controller at 300200 {
> +			compatible = "zhihe,a210-peri-clk";
> +			reg = <0x0 0x00300200 0x0 0x4>,
> +			      <0x0 0x02010200 0x0 0x8>,
> +			      <0x0 0x08400200 0x0 0x8>,
> +			      <0x0 0x00540200 0x0 0x4>,
> +			      <0x0 0x27420200 0x0 0x200>;

Same here, particularly things that are only a single word wide...

> +			reg-names = "peri0-sysreg", "peri1-sysreg",
> +				    "peri2-sysreg", "peri3-sysreg", "tee-crg";
> +			#clock-cells = <1>;
> +		};

> +		clk_aon: clock-controller at 30844000 {
> +			compatible = "zhihe,a210-aon-clk";
> +			reg = <0 0x30844000 0 0x1c>;

0x1c is also suspiciously narrow, but believable. Is there a register
map for this device available somewhere (ideally in english, but I
suppose machine translation will do a sufficient job) so that I can try
to understand how this device should be modelled?

Thanks,
Conor.

> +			#clock-cells = <1>;
> +			clocks = <&aon_110m>, <&osc_24m>, <&aon_rc>, <&osc_32k>;
> +			clock-names = "high", "osc", "rc", "rtc";
> +		};
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