[PATCH 13/18] riscv: dts: zhihe: add A210 core support
Han Gao via B4 Relay
devnull+gaohan.iscas.ac.cn at kernel.org
Wed Oct 21 12:53:33 PDT 2026
From: Zhiguo Zhu <zhiguo.zhu at linux.alibaba.com>
Add the A210 CPU clusters, caches, interrupt controllers and control
blocks.
Signed-off-by: Zhiguo Zhu <zhiguo.zhu at linux.alibaba.com>
Co-developed-by: Han Gao <gaohan at iscas.ac.cn>
Signed-off-by: Han Gao <gaohan at iscas.ac.cn>
---
arch/riscv/boot/dts/zhihe/a210.dtsi | 495 ++++++++++++++++++++++++++++++++++++
1 file changed, 495 insertions(+)
diff --git a/arch/riscv/boot/dts/zhihe/a210.dtsi b/arch/riscv/boot/dts/zhihe/a210.dtsi
new file mode 100644
index 000000000000..bbad51a3edb0
--- /dev/null
+++ b/arch/riscv/boot/dts/zhihe/a210.dtsi
@@ -0,0 +1,495 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Copyright (C) 2021 Alibaba Group Holding Limited.
+ */
+
+#include <dt-bindings/clock/zhihe,a210-clk.h>
+#include <dt-bindings/clock/zhihe,a210-aon-clk.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/reset/zhihe,a210-resets.h>
+
+/ {
+ compatible = "zhihe,a210";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aon_rc: clock-aon-rc {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <26000000>;
+ };
+
+ osc_24m: clock-osc-24m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ clock-output-names = "osc-24m";
+ };
+
+ osc_32k: clock-osc-32k {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "osc-32k";
+ };
+
+ aon_110m: clock-osc-110m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <110000000>;
+ clock-output-names = "aon-110m";
+ };
+
+ rc_24m: clock-rc-24m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ clock-output-names = "rc-24m";
+ };
+
+ cpus: cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ timebase-frequency = <24000000>;
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&c908_0>;
+ };
+
+ core1 {
+ cpu = <&c908_1>;
+ };
+
+ core2 {
+ cpu = <&c908_2>;
+ };
+
+ core3 {
+ cpu = <&c908_3>;
+ };
+ };
+
+ cluster1 {
+ core0 {
+ cpu = <&c920_4>;
+ };
+
+ core1 {
+ cpu = <&c920_5>;
+ };
+
+ core2 {
+ cpu = <&c920_6>;
+ };
+
+ core3 {
+ cpu = <&c920_7>;
+ };
+ };
+ };
+
+ c0_l2_cache: l2-cache0 {
+ compatible = "cache";
+ cache-block-size = <64>;
+ cache-level = <2>;
+ cache-sets = <512>;
+ cache-size = <524288>;
+ cache-unified;
+ };
+
+ c1_l2_cache: l2-cache1 {
+ compatible = "cache";
+ cache-block-size = <64>;
+ cache-level = <2>;
+ cache-sets = <1024>;
+ cache-size = <1048576>;
+ cache-unified;
+ };
+
+ c908_0: cpu at 0 {
+ device_type = "cpu";
+ compatible = "thead,c908", "riscv";
+ reg = <0>;
+ clocks = <&clk C908_CPU_TO_CDE_CLK_MUX>;
+ d-cache-block-size = <64>;
+ d-cache-sets = <256>;
+ d-cache-size = <32768>;
+ i-cache-block-size = <64>;
+ i-cache-sets = <256>;
+ i-cache-size = <32768>;
+ mmu-type = "riscv,sv39";
+ next-level-cache = <&c0_l2_cache>;
+ riscv,cbom-block-size = <64>;
+ riscv,cbop-block-size = <64>;
+ riscv,cboz-block-size = <64>;
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+ "b", "v", "sscofpmf", "sstc",
+ "svpbmt", "zba", "zbb", "zbc",
+ "zbs", "zicbom", "zicbop",
+ "zicboz", "zicntr", "zicsr",
+ "zifencei", "zihpm";
+
+ cpu0_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+ };
+
+ c908_1: cpu at 1 {
+ device_type = "cpu";
+ compatible = "thead,c908", "riscv";
+ reg = <1>;
+ d-cache-block-size = <64>;
+ d-cache-sets = <256>;
+ d-cache-size = <32768>;
+ i-cache-block-size = <64>;
+ i-cache-sets = <256>;
+ i-cache-size = <32768>;
+ mmu-type = "riscv,sv39";
+ next-level-cache = <&c0_l2_cache>;
+ riscv,cbom-block-size = <64>;
+ riscv,cbop-block-size = <64>;
+ riscv,cboz-block-size = <64>;
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+ "b", "v", "sscofpmf", "sstc",
+ "svpbmt", "zba", "zbb", "zbc",
+ "zbs", "zicbom", "zicbop",
+ "zicboz", "zicntr", "zicsr",
+ "zifencei", "zihpm";
+
+ cpu1_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+ };
+
+ c908_2: cpu at 2 {
+ device_type = "cpu";
+ compatible = "thead,c908", "riscv";
+ reg = <2>;
+ d-cache-block-size = <64>;
+ d-cache-sets = <256>;
+ d-cache-size = <32768>;
+ i-cache-block-size = <64>;
+ i-cache-sets = <256>;
+ i-cache-size = <32768>;
+ mmu-type = "riscv,sv39";
+ next-level-cache = <&c0_l2_cache>;
+ riscv,cbom-block-size = <64>;
+ riscv,cbop-block-size = <64>;
+ riscv,cboz-block-size = <64>;
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+ "b", "v", "sscofpmf", "sstc",
+ "svpbmt", "zba", "zbb", "zbc",
+ "zbs", "zicbom", "zicbop",
+ "zicboz", "zicntr", "zicsr",
+ "zifencei", "zihpm";
+
+ cpu2_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+ };
+
+ c908_3: cpu at 3 {
+ device_type = "cpu";
+ compatible = "thead,c908", "riscv";
+ reg = <3>;
+ d-cache-block-size = <64>;
+ d-cache-sets = <256>;
+ d-cache-size = <32768>;
+ i-cache-block-size = <64>;
+ i-cache-sets = <256>;
+ i-cache-size = <32768>;
+ mmu-type = "riscv,sv39";
+ next-level-cache = <&c0_l2_cache>;
+ riscv,cbom-block-size = <64>;
+ riscv,cbop-block-size = <64>;
+ riscv,cboz-block-size = <64>;
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+ "b", "v", "sscofpmf", "sstc",
+ "svpbmt", "zba", "zbb", "zbc",
+ "zbs", "zicbom", "zicbop",
+ "zicboz", "zicntr", "zicsr",
+ "zifencei", "zihpm";
+
+ cpu3_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+ };
+
+ c920_4: cpu at 4 {
+ device_type = "cpu";
+ compatible = "thead,c920", "riscv";
+ reg = <4>;
+ clocks = <&clk C920_CPU_TO_CDE_CLK_MUX>;
+ d-cache-block-size = <64>;
+ d-cache-sets = <512>;
+ d-cache-size = <65536>;
+ i-cache-block-size = <64>;
+ i-cache-sets = <512>;
+ i-cache-size = <65536>;
+ mmu-type = "riscv,sv39";
+ next-level-cache = <&c1_l2_cache>;
+ riscv,cbom-block-size = <64>;
+ riscv,cbop-block-size = <64>;
+ riscv,cboz-block-size = <64>;
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+ "b", "v", "sscofpmf", "sstc",
+ "svpbmt", "zba", "zbb", "zbc",
+ "zbs", "zicbom", "zicbop",
+ "zicboz", "zicntr", "zicsr",
+ "zifencei", "zihpm";
+
+ cpu4_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+ };
+
+ c920_5: cpu at 5 {
+ device_type = "cpu";
+ compatible = "thead,c920", "riscv";
+ reg = <5>;
+ d-cache-block-size = <64>;
+ d-cache-sets = <512>;
+ d-cache-size = <65536>;
+ i-cache-block-size = <64>;
+ i-cache-sets = <512>;
+ i-cache-size = <65536>;
+ mmu-type = "riscv,sv39";
+ next-level-cache = <&c1_l2_cache>;
+ riscv,cbom-block-size = <64>;
+ riscv,cbop-block-size = <64>;
+ riscv,cboz-block-size = <64>;
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+ "b", "v", "sscofpmf", "sstc",
+ "svpbmt", "zba", "zbb", "zbc",
+ "zbs", "zicbom", "zicbop",
+ "zicboz", "zicntr", "zicsr",
+ "zifencei", "zihpm";
+
+ cpu5_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+ };
+
+ c920_6: cpu at 6 {
+ device_type = "cpu";
+ compatible = "thead,c920", "riscv";
+ reg = <6>;
+ d-cache-block-size = <64>;
+ d-cache-sets = <512>;
+ d-cache-size = <65536>;
+ i-cache-block-size = <64>;
+ i-cache-sets = <512>;
+ i-cache-size = <65536>;
+ mmu-type = "riscv,sv39";
+ next-level-cache = <&c1_l2_cache>;
+ riscv,cbom-block-size = <64>;
+ riscv,cbop-block-size = <64>;
+ riscv,cboz-block-size = <64>;
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+ "b", "v", "sscofpmf", "sstc",
+ "svpbmt", "zba", "zbb", "zbc",
+ "zbs", "zicbom", "zicbop",
+ "zicboz", "zicntr", "zicsr",
+ "zifencei", "zihpm";
+
+ cpu6_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+ };
+
+ c920_7: cpu at 7 {
+ device_type = "cpu";
+ compatible = "thead,c920", "riscv";
+ reg = <7>;
+ d-cache-block-size = <64>;
+ d-cache-sets = <512>;
+ d-cache-size = <65536>;
+ i-cache-block-size = <64>;
+ i-cache-sets = <512>;
+ i-cache-size = <65536>;
+ mmu-type = "riscv,sv39";
+ next-level-cache = <&c1_l2_cache>;
+ riscv,cbom-block-size = <64>;
+ riscv,cbop-block-size = <64>;
+ riscv,cboz-block-size = <64>;
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+ "b", "v", "sscofpmf", "sstc",
+ "svpbmt", "zba", "zbb", "zbc",
+ "zbs", "zicbom", "zicbop",
+ "zicboz", "zicntr", "zicsr",
+ "zifencei", "zihpm";
+
+ cpu7_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+ };
+ };
+
+ soc {
+ compatible = "simple-bus";
+ ranges;
+ #address-cells = <2>;
+ dma-noncoherent;
+ #size-cells = <2>;
+
+ clk: clock-controller at 260000 {
+ compatible = "zhihe,a210-clk";
+ reg = <0x0 0x00260000 0x0 0x1000>,
+ <0x0 0x00250000 0x0 0x1000>,
+ <0x0 0x10141600 0x0 0x100>,
+ <0x0 0x10141400 0x0 0x100>,
+ <0x0 0x04810000 0x0 0x1000>,
+ <0x0 0x05810000 0x0 0x1000>,
+ <0x0 0x04900000 0x0 0x1000>,
+ <0x0 0x20250000 0x0 0x1000>,
+ <0x0 0x10140000 0x0 0xe00>;
+ reg-names = "pll-wrap", "top-crg", "cpu-ss-clk-sysreg",
+ "cpu-ss-cpu-pll", "ddr0-sysreg",
+ "ddr1-sysreg", "slc-dual-sysreg",
+ "top-crg-t", "cpu-ss-ccu";
+ #clock-cells = <1>;
+ clocks = <&osc_32k>, <&osc_24m>, <&rc_24m>;
+ clock-names = "osc-32k", "osc-24m", "rc-24m";
+ };
+
+ clk_peri: clock-controller at 300200 {
+ compatible = "zhihe,a210-peri-clk";
+ reg = <0x0 0x00300200 0x0 0x4>,
+ <0x0 0x02010200 0x0 0x8>,
+ <0x0 0x08400200 0x0 0x8>,
+ <0x0 0x00540200 0x0 0x4>,
+ <0x0 0x27420200 0x0 0x200>;
+ reg-names = "peri0-sysreg", "peri1-sysreg",
+ "peri2-sysreg", "peri3-sysreg", "tee-crg";
+ #clock-cells = <1>;
+ };
+
+ peri3_padctrl: pinctrl at 542000 {
+ compatible = "zhihe,a210-peri3-pinctrl";
+ reg = <0x0 0x00542000 0x0 0x1000>;
+ clocks = <&clk_peri PERI3_PAD_CTRL_PCLK_EN>;
+ clock-names = "pclk";
+
+ status = "disabled";
+ };
+
+ rst_peri1: reset-controller at 2010400 {
+ compatible = "zhihe,a210-peri1-reset";
+ reg = <0x0 0x02010400 0x0 0x200>;
+ #reset-cells = <1>;
+ };
+
+ peri1_padctrl: pinctrl at 2026000 {
+ compatible = "zhihe,a210-peri1-pinctrl";
+ reg = <0x0 0x02026000 0x0 0x1000>;
+ clocks = <&clk_peri PERI1_PAD_CTRL_PCLK_EN>;
+ clock-names = "pclk";
+
+ status = "disabled";
+ };
+
+ rst_peri2: reset-controller at 8400400 {
+ compatible = "zhihe,a210-peri2-reset";
+ reg = <0x0 0x08400400 0x0 0x200>;
+ #reset-cells = <1>;
+ };
+
+ peri2_padctrl: pinctrl at 8411000 {
+ compatible = "zhihe,a210-peri2-pinctrl";
+ reg = <0x0 0x08411000 0x0 0x1000>;
+ clocks = <&clk_peri PERI2_PAD_CTRL_PCLK_EN>;
+ clock-names = "pclk";
+
+ status = "disabled";
+ };
+
+ intc: interrupt-controller at 18000000 {
+ compatible = "zhihe,a210-plic", "thead,c900-plic";
+ reg = <0x0 0x18000000 0x0 0x04000000>;
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ interrupts-extended = <&cpu0_intc 0xffffffff>,
+ <&cpu0_intc 9>,
+ <&cpu1_intc 0xffffffff>,
+ <&cpu1_intc 9>,
+ <&cpu2_intc 0xffffffff>,
+ <&cpu2_intc 9>,
+ <&cpu3_intc 0xffffffff>,
+ <&cpu3_intc 9>,
+ <&cpu4_intc 0xffffffff>,
+ <&cpu4_intc 9>,
+ <&cpu5_intc 0xffffffff>,
+ <&cpu5_intc 9>,
+ <&cpu6_intc 0xffffffff>,
+ <&cpu6_intc 9>,
+ <&cpu7_intc 0xffffffff>,
+ <&cpu7_intc 9>;
+ riscv,ndev = <351>;
+ };
+
+ clint0: clint at 1c000000 {
+ compatible = "zhihe,a210-clint", "thead,c900-clint";
+ reg = <0x0 0x1c000000 0x0 0x0000d800>;
+ interrupts-extended = <&cpu0_intc 3>,
+ <&cpu0_intc 7>,
+ <&cpu1_intc 3>,
+ <&cpu1_intc 7>,
+ <&cpu2_intc 3>,
+ <&cpu2_intc 7>,
+ <&cpu3_intc 3>,
+ <&cpu3_intc 7>,
+ <&cpu4_intc 3>,
+ <&cpu4_intc 7>,
+ <&cpu5_intc 3>,
+ <&cpu5_intc 7>,
+ <&cpu6_intc 3>,
+ <&cpu6_intc 7>,
+ <&cpu7_intc 3>,
+ <&cpu7_intc 7>;
+ };
+
+ clk_aon: clock-controller at 30844000 {
+ compatible = "zhihe,a210-aon-clk";
+ reg = <0 0x30844000 0 0x1c>;
+ #clock-cells = <1>;
+ clocks = <&aon_110m>, <&osc_24m>, <&aon_rc>, <&osc_32k>;
+ clock-names = "high", "osc", "rc", "rtc";
+ };
+
+ aon_padctrl: pinctrl at 30848000 {
+ compatible = "zhihe,a210-aon-pinctrl";
+ reg = <0x0 0x30848000 0x0 0x2000>;
+ clocks = <&clk_aon A210_AON_SYS_CLK>;
+ clock-names = "pclk";
+
+ status = "disabled";
+ };
+ };
+};
--
2.55.0
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