[PATCH] riscv: fix RVG_SYSTEM_CSR_MASK width mask

[Paul Walmsley]

On Fri, 11 Sep 2026, Aurelien Jarno wrote:

> RVG_SYSTEM_CSR_MASK should be 12 bits [31:20], shifted down by 20 bits.
> Replace GENMASK(12, 0) by GENMASK(11, 0).
> 
> Fixes: cd054837243b ("riscv: Allocate user's vector context in the first-use trap")
> Signed-off-by: Aurelien Jarno <aurelien at aurel32.net>

Thanks, queued for v7.4.


- Paul