[PATCH] riscv: fix RVG_SYSTEM_CSR_MASK width mask

[Jisheng Zhang]

On Fri, Sep 11, 2026 at 09:42:33PM +0200, Aurelien Jarno wrote:
> RVG_SYSTEM_CSR_MASK should be 12 bits [31:20], shifted down by 20 bits.
> Replace GENMASK(12, 0) by GENMASK(11, 0).
> 
> Fixes: cd054837243b ("riscv: Allocate user's vector context in the first-use trap")
> Signed-off-by: Aurelien Jarno <aurelien at aurel32.net>

Reviewed-by: Jisheng Zhang <jszhang at kernel.org>
> ---
>  arch/riscv/include/asm/insn.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/riscv/include/asm/insn.h b/arch/riscv/include/asm/insn.h
> index c3005573e8c9..ad348d8b8857 100644
> --- a/arch/riscv/include/asm/insn.h
> +++ b/arch/riscv/include/asm/insn.h
> @@ -142,7 +142,7 @@
>  #define RVG_OPCODE_JAL		0x6f
>  #define RVG_OPCODE_SYSTEM	0x73
>  #define RVG_SYSTEM_CSR_OFF	20
> -#define RVG_SYSTEM_CSR_MASK	GENMASK(12, 0)
> +#define RVG_SYSTEM_CSR_MASK	GENMASK(11, 0)
>  
>  /* parts of opcode for RVF, RVD and RVQ */
>  #define RVFDQ_FL_FS_WIDTH_OFF	12
> -- 
> 2.53.0
> 
> 
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