[PATCH v2 05/19] cache: ax45mp_cache: standardize macro naming for LLC and L1D registers

[Mina Hui-Min Chou]

Rename macros to follow a consistent naming convention:
ANDES_{LLC|L1D}_{REG_}CCTL_{operation}_{target}
- LLC or L1D: which cache level
- REG_: present for register offset macros
- CCTL: cache control operation
- target: C0 for core 0 base, BY_CORE(n) for per-core variants

This is a mechanical rename with no functional change:
- ANDES_LLC_REG_C0_* -> ANDES_LLC_REG_CCTL_*_C0
- ANDES_LLC_REG_CN_* -> ANDES_LLC_REG_CCTL_*_BY_CORE(n)
- ANDES_CCTL_L1D_*   -> ANDES_L1D_CCTL_*
- ANDES_CCTL_LLC_*   -> ANDES_LLC_CCTL_*
- Use GENMASK(3, 0) instead of 0xf for ANDES_LLC_CCTL_STATUS_MASK_C0

Signed-off-by: Mina Hui-Min Chou <minachou at andestech.com>
---
 drivers/cache/ax45mp_cache.c | 55 ++++++++++++++++++------------------
 1 file changed, 27 insertions(+), 28 deletions(-)

diff --git a/drivers/cache/ax45mp_cache.c b/drivers/cache/ax45mp_cache.c
index b3d6f6a11cfc..61730e218afa 100644
--- a/drivers/cache/ax45mp_cache.c
+++ b/drivers/cache/ax45mp_cache.c
@@ -16,34 +16,33 @@
 
 /* LLC registers */
 #define ANDES_LLC_REG_CTL_OFFSET		0x8
+#define ANDES_LLC_REG_CCTL_CMD_OFFSET_C0	0x40
+#define ANDES_LLC_REG_CCTL_ACC_OFFSET_C0	0x48
+#define ANDES_LLC_REG_CCTL_STATUS_OFFSET_C0	0x80
 
-#define ANDES_LLC_REG_C0_CMD_OFFSET		0x40
-#define ANDES_LLC_REG_C0_ACC_OFFSET		0x48
-#define ANDES_LLC_REG_STATUS_OFFSET		0x80
-
-/* D-cache operation */
-#define ANDES_CCTL_L1D_VA_INVAL		0 /* Invalidate an L1 cache entry */
-#define ANDES_CCTL_L1D_VA_WB			1 /* Write-back an L1 cache entry */
+/* L1 D-cache operation */
+#define ANDES_L1D_CCTL_VA_INVAL			0x0 /* Invalidate an L1 cache entry */
+#define ANDES_L1D_CCTL_VA_WB			0x1 /* Write-back an L1 cache entry */
 
 /* LLC CCTL status */
-#define ANDES_CCTL_LLC_STATUS_IDLE		0
+#define ANDES_LLC_CCTL_STATUS_IDLE		0x0
 
 /* LLC CCTL status cores mask */
-#define ANDES_CCTL_LLC_STATUS_C0_MASK		0xf
+#define ANDES_LLC_CCTL_STATUS_MASK_C0		GENMASK(3, 0)
 
 /* LLC operation */
-#define ANDES_CCTL_LLC_PA_INVAL			0x8 /* Invalidate an LLC entry */
-#define ANDES_CCTL_LLC_PA_WB			0x9 /* Write-back an LLC entry */
+#define ANDES_LLC_CCTL_PA_INVAL			0x8 /* Invalidate an LLC entry */
+#define ANDES_LLC_CCTL_PA_WB			0x9 /* Write-back an LLC entry */
 
-#define ANDES_LLC_REG_PER_CORE_OFFSET		0x10
-#define ANDES_CCTL_LLC_STATUS_PER_CORE_OFFSET	4
+#define ANDES_LLC_REG_CCTL_CORE_OFFSET		0x10
+#define ANDES_LLC_CCTL_STATUS_MASK_CORE_OFFSET	0x4
 
-#define ANDES_LLC_REG_CN_CMD_OFFSET(n)	\
-	(ANDES_LLC_REG_C0_CMD_OFFSET + ((n) * ANDES_LLC_REG_PER_CORE_OFFSET))
-#define ANDES_LLC_REG_CN_ACC_OFFSET(n)	\
-	(ANDES_LLC_REG_C0_ACC_OFFSET + ((n) * ANDES_LLC_REG_PER_CORE_OFFSET))
-#define ANDES_CCTL_LLC_STATUS_CN_MASK(n)	\
-	(ANDES_CCTL_LLC_STATUS_C0_MASK << ((n) * ANDES_CCTL_LLC_STATUS_PER_CORE_OFFSET))
+#define ANDES_LLC_REG_CCTL_CMD_OFFSET_BY_CORE(n)	\
+	(ANDES_LLC_REG_CCTL_CMD_OFFSET_C0 + ((n) * ANDES_LLC_REG_CCTL_CORE_OFFSET))
+#define ANDES_LLC_REG_CCTL_ACC_OFFSET_BY_CORE(n)	\
+	(ANDES_LLC_REG_CCTL_ACC_OFFSET_C0 + ((n) * ANDES_LLC_REG_CCTL_CORE_OFFSET))
+#define ANDES_LLC_CCTL_STATUS_MASK_BY_CORE(n)	\
+	(ANDES_LLC_CCTL_STATUS_MASK_C0 << ((n) * ANDES_LLC_CCTL_STATUS_MASK_CORE_OFFSET))
 
 #define ANDES_CACHE_LINE_SIZE			64
 
@@ -57,7 +56,7 @@ static struct andes_priv andes_priv;
 /* LLC operations */
 static inline uint32_t andes_cpu_llc_get_cctl_status(void)
 {
-	return readl(andes_priv.llc_base + ANDES_LLC_REG_STATUS_OFFSET);
+	return readl(andes_priv.llc_base + ANDES_LLC_REG_CCTL_STATUS_OFFSET_C0);
 }
 
 static void andes_cpu_cache_operation(unsigned long start, unsigned long end,
@@ -73,11 +72,11 @@ static void andes_cpu_cache_operation(unsigned long start, unsigned long end,
 		csr_write(CSR_UCCTLCOMMAND, l1_op);
 
 		pa = virt_to_phys((void *)start);
-		writel(pa, base + ANDES_LLC_REG_CN_ACC_OFFSET(mhartid));
-		writel(llc_op, base + ANDES_LLC_REG_CN_CMD_OFFSET(mhartid));
+		writel(pa, base + ANDES_LLC_REG_CCTL_ACC_OFFSET_BY_CORE(mhartid));
+		writel(llc_op, base + ANDES_LLC_REG_CCTL_CMD_OFFSET_BY_CORE(mhartid));
 		while ((andes_cpu_llc_get_cctl_status() &
-			ANDES_CCTL_LLC_STATUS_CN_MASK(mhartid)) !=
-			ANDES_CCTL_LLC_STATUS_IDLE)
+			ANDES_LLC_CCTL_STATUS_MASK_BY_CORE(mhartid)) !=
+			ANDES_LLC_CCTL_STATUS_IDLE)
 			;
 
 		start += line_size;
@@ -87,15 +86,15 @@ static void andes_cpu_cache_operation(unsigned long start, unsigned long end,
 /* Write-back L1 and LLC entry */
 static inline void andes_cpu_dcache_wb_range(unsigned long start, unsigned long end)
 {
-	andes_cpu_cache_operation(start, end, ANDES_CCTL_L1D_VA_WB,
-				  ANDES_CCTL_LLC_PA_WB);
+	andes_cpu_cache_operation(start, end, ANDES_L1D_CCTL_VA_WB,
+				  ANDES_LLC_CCTL_PA_WB);
 }
 
 /* Invalidate the L1 and LLC entry */
 static inline void andes_cpu_dcache_inval_range(unsigned long start, unsigned long end)
 {
-	andes_cpu_cache_operation(start, end, ANDES_CCTL_L1D_VA_INVAL,
-				  ANDES_CCTL_LLC_PA_INVAL);
+	andes_cpu_cache_operation(start, end, ANDES_L1D_CCTL_VA_INVAL,
+				  ANDES_LLC_CCTL_PA_INVAL);
 }
 
 static void andes_dma_cache_inv(phys_addr_t paddr, size_t size)
-- 
2.34.1