[PATCH v2 04/19] cache: ax45mp_cache: add shared header for Andes CSRs

[Mina Hui-Min Chou]

Add linux/soc/andes/csr.h as a central place for Andes vendor-specific
CSR definitions, and update the cache driver to use CSR_UCCTLBEGINADDR
and CSR_UCCTLCOMMAND from the new header instead of local definitions.
More Andes CSR definitions will be added here as needed.

Signed-off-by: Mina Hui-Min Chou <minachou at andestech.com>
---
 drivers/cache/ax45mp_cache.c  |  8 +++-----
 include/linux/soc/andes/csr.h | 12 ++++++++++++
 2 files changed, 15 insertions(+), 5 deletions(-)
 create mode 100644 include/linux/soc/andes/csr.h

diff --git a/drivers/cache/ax45mp_cache.c b/drivers/cache/ax45mp_cache.c
index 0ee8218d5a82..b3d6f6a11cfc 100644
--- a/drivers/cache/ax45mp_cache.c
+++ b/drivers/cache/ax45mp_cache.c
@@ -10,6 +10,7 @@
 #include <linux/dma-direction.h>
 #include <linux/of_address.h>
 #include <linux/of_platform.h>
+#include <linux/soc/andes/csr.h>
 
 #include <asm/dma-noncoherent.h>
 
@@ -44,9 +45,6 @@
 #define ANDES_CCTL_LLC_STATUS_CN_MASK(n)	\
 	(ANDES_CCTL_LLC_STATUS_C0_MASK << ((n) * ANDES_CCTL_LLC_STATUS_PER_CORE_OFFSET))
 
-#define ANDES_CCTL_REG_UCCTLBEGINADDR_NUM	0x80b
-#define ANDES_CCTL_REG_UCCTLCOMMAND_NUM	0x80c
-
 #define ANDES_CACHE_LINE_SIZE			64
 
 struct andes_priv {
@@ -71,8 +69,8 @@ static void andes_cpu_cache_operation(unsigned long start, unsigned long end,
 	unsigned long pa;
 
 	while (end > start) {
-		csr_write(ANDES_CCTL_REG_UCCTLBEGINADDR_NUM, start);
-		csr_write(ANDES_CCTL_REG_UCCTLCOMMAND_NUM, l1_op);
+		csr_write(CSR_UCCTLBEGINADDR, start);
+		csr_write(CSR_UCCTLCOMMAND, l1_op);
 
 		pa = virt_to_phys((void *)start);
 		writel(pa, base + ANDES_LLC_REG_CN_ACC_OFFSET(mhartid));
diff --git a/include/linux/soc/andes/csr.h b/include/linux/soc/andes/csr.h
new file mode 100644
index 000000000000..3214b4b08a46
--- /dev/null
+++ b/include/linux/soc/andes/csr.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2026 Andes Technology Corporation.
+ */
+#ifndef __LINUX_SOC_ANDES_CSR_H
+#define __LINUX_SOC_ANDES_CSR_H
+
+/* User mode control registers */
+#define CSR_UCCTLBEGINADDR		0x80b
+#define CSR_UCCTLCOMMAND		0x80c
+
+#endif /* !__LINUX_SOC_ANDES_CSR_H */
-- 
2.34.1