[PATCH v3 4/7] dt-bindings: timer: Add RISC-V ACLINT mtimer bindings

[Joel Stanley]

Document the RISC-V ACLINT mtimer and mtimecmp hardware, as described
by the riscv-aclint specification, commit 4e570bfd3201f2 [2].

Multiple vendors are shipping silicon with the hardware as described
by the specification, which was abandoned[1] as a standalone spec at
v1.0-rc4.  As we have multiple instances of hardware that implement
the spec, the widespread implementation of the spec is de facto
ratification, providing a stationary target for the bindings to document
and an exception to the policy of not accepting things that are
pre-ratification.

[1] https://lists.riscv.org/g/tech-aia/topic/connections_between_aia_and/107177435
[2] https://github.com/riscvarchive/riscv-aclint/blob/4e570bfd3201f2c09e5afd290b5091526b0f099a/riscv-aclint.adoc

Signed-off-by: Joel Stanley <joel at jms.id.au>
---
v3:
  - Rework commit message following discussion at LPC
  - Add reg-names, rework description, fix example
---
 MAINTAINERS                                   |  1 +
 .../bindings/timer/riscv,aclint-mtimer.yaml   | 56 +++++++++++++++++++
 2 files changed, 57 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/timer/riscv,aclint-mtimer.yaml

diff --git a/MAINTAINERS b/MAINTAINERS
index 93abbb315065..403875d5932e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -24185,6 +24185,7 @@ S:	Maintained
 T:	git git://git.kernel.org/pub/scm/linux/kernel/git/tenstorrent/linux.git
 F:	Documentation/devicetree/bindings/clock/tenstorrent,atlantis-prcm-rcpu.yaml
 F:	Documentation/devicetree/bindings/riscv/tenstorrent.yaml
+F:	Documentation/devicetree/bindings/timer/riscv,aclint-mtimer.yaml
 F:	arch/riscv/boot/dts/tenstorrent/
 F:	drivers/clk/tenstorrent/
 F:	drivers/reset/reset-tenstorrent-atlantis.c
diff --git a/Documentation/devicetree/bindings/timer/riscv,aclint-mtimer.yaml b/Documentation/devicetree/bindings/timer/riscv,aclint-mtimer.yaml
new file mode 100644
index 000000000000..e6f3d08d4f93
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/riscv,aclint-mtimer.yaml
@@ -0,0 +1,56 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/timer/riscv,aclint-mtimer.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: RISC-V Advanced Core Local Interruptor (ACLINT) timer
+
+maintainers:
+  - Joel Stanley <jms at oss.tenstorrent.com>
+
+description:
+  The RISC-V ACLINT specification defines a set of memory mapped devices which
+  provide timer functionality for each hart on a multi-hart RISC-V platform.
+  The mtimer device has a single mtime register and one mtimecmp register per
+  hart. The specification is at https://github.com/riscvarchive/riscv-aclint/
+
+properties:
+  compatible:
+    items:
+      - enum:
+          - tenstorrent,atlantis-aclint-mtimer
+      - const: riscv,aclint-mtimer
+
+  reg:
+    items:
+      - description: mtime register
+      - description: mtimecmp registers
+
+  reg-names:
+    items:
+      - const: mtime
+      - const: mtimecmp
+
+  interrupts-extended:
+    minItems: 1
+    maxItems: 4095
+
+required:
+  - compatible
+  - reg
+
+additionalProperties: false
+
+examples:
+  - |
+    timer at a2180000 {
+      compatible = "tenstorrent,atlantis-aclint-mtimer", "riscv,aclint-mtimer";
+      reg = <0xa2180000 0x8000>, <0xa2188000 0x8000>;
+      reg-names = "mtime", "mtimecmp";
+      interrupts-extended = <&cpu1intc 7>,
+                            <&cpu2intc 7>,
+                            <&cpu3intc 7>,
+                            <&cpu4intc 7>;
+    };
+...
-- 
2.47.3