[PATCH v3 3/7] dt-bindings: riscv: cpus: Add Tenstorrent Ascalon

[Joel Stanley]

Add Tenstorrent Ascalon microarchitecture and the Tenstorrent Ascalon-XG
core.

Acked-by: Conor Dooley <conor.dooley at microchip.com>
Reviewed-by: Drew Fustini <fustini at kernel.org>
Signed-off-by: Joel Stanley <joel at jms.id.au>
---
v3: No changes, pick up review tags
---
 Documentation/devicetree/bindings/riscv/cpus.yaml | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index 0da219ae6769..2d2e4606a53e 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -75,6 +75,11 @@ properties:
               - sifive,x280
           - const: sifive,rocket0
           - const: riscv
+      - items:
+          - enum:
+              - tenstorrent,ascalon-xg
+          - const: tenstorrent,ascalon
+          - const: riscv
       - const: riscv    # Simulator only
     description:
       Identifies that the hart uses the RISC-V instruction set
-- 
2.47.3