[PATCH v2 5/8] dt-bindings: interrupt-controller: Add MIPS P8700 ACLINT MSWI

[Conor Dooley]

On Tue, Nov 03, 2026 at 04:11:29PM +0100, Aleksa Paunovic via B4 Relay wrote:
> From: Aleksa Paunovic <aleksa.paunovic at htecgroup.com>
> 
> Document the aclint mswi compatible for the MIPS P8700.
> 
> Signed-off-by: Aleksa Paunovic <aleksa.paunovic at htecgroup.com>

Again, same comment :)

Acked-by: Conor Dooley <conor.dooley at microchip.com>
pw-bot: not-applicable

> ---
>  .../bindings/interrupt-controller/thead,c900-aclint-mswi.yaml | 11 +++++++++++
>  1 file changed, 11 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-mswi.yaml b/Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-mswi.yaml
> index 62fd220e126e650e3800d8eee2a749fdbbde6108..ca91b650caab8927b3a4ed91f1f7f142e3790a97 100644
> --- a/Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-mswi.yaml
> +++ b/Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-mswi.yaml
> @@ -21,6 +21,7 @@ properties:
>            - enum:
>                - anlogic,dr1v90-aclint-mswi
>            - const: nuclei,ux900-aclint-mswi
> +      - const: gf,mips-p8700-aclint-mswi
>  
>    reg:
>      maxItems: 1
> @@ -46,4 +47,14 @@ examples:
>                              <&cpu4intc 3>;
>        reg = <0x94000000 0x00010000>;
>      };
> +
> +  - |
> +    mswi at 16150000 {
> +        compatible = "gf,mips-p8700-aclint-mswi";
> +        reg = <0x16150000 0x4000>;
> +        interrupts-extended = <&cpu1intc 3>,
> +                              <&cpu2intc 3>,
> +                              <&cpu3intc 3>,
> +                              <&cpu4intc 3>;
> +    };
>  ...
> 
> -- 
> 2.43.0
> 
> 
> 
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