[PATCH net-next v3 3/3] riscv: dts: eswin: eic7700-hifive-premier-p550: enable Ethernet controller

[李志]

> -----原始邮件-----
> 发件人: "Yao Zi" <me at ziyao.cc>
> 发送时间:2026-03-03 18:32:38 (星期二)
> 收件人: lizhi2 at eswincomputing.com, devicetree at vger.kernel.org, andrew+netdev at lunn.ch, davem at davemloft.net, edumazet at google.com, kuba at kernel.org, robh at kernel.org, krzk+dt at kernel.org, conor+dt at kernel.org, netdev at vger.kernel.org, pabeni at redhat.com, mcoquelin.stm32 at gmail.com, alexandre.torgue at foss.st.com, rmk+kernel at armlinux.org.uk, wens at kernel.org, pjw at kernel.org, palmer at dabbelt.com, aou at eecs.berkeley.edu, alex at ghiti.fr, linux-riscv at lists.infradead.org, linux-stm32 at st-md-mailman.stormreply.com, linux-arm-kernel at lists.infradead.org, linux-kernel at vger.kernel.org
> 抄送: ningyu at eswincomputing.com, linmin at eswincomputing.com, pinkesh.vaghela at einfochips.com, pritesh.patel at einfochips.com, weishangjuan at eswincomputing.com
> 主题: Re: [PATCH net-next v3 3/3] riscv: dts: eswin: eic7700-hifive-premier-p550: enable Ethernet controller
> 
> On Tue, Mar 03, 2026 at 02:17:32PM +0800, lizhi2 at eswincomputing.com wrote:
> > From: Zhi Li <lizhi2 at eswincomputing.com>
> > 
> > Enable the on-board Gigabit Ethernet controller on the
> > HiFive Premier P550 development board.
> > 
> > Signed-off-by: Zhi Li <lizhi2 at eswincomputing.com>
> > ---
> >  .../dts/eswin/eic7700-hifive-premier-p550.dts | 50 +++++++++++++++++
> >  arch/riscv/boot/dts/eswin/eic7700.dtsi        | 54 +++++++++++++++++++
> >  2 files changed, 104 insertions(+)
> > 
> > diff --git a/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts b/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
> > index 131ed1fc6b2e..d558f0fdfb38 100644
> > --- a/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
> > +++ b/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
> 
> ...
> 
> > @@ -20,6 +22,54 @@ chosen {
> >  	};
> >  };
> >  
> > +&gmac0 {
> > +	phy-handle = <&gmac0_phy0>;
> > +	phy-mode = "rgmii-id";
> > +	pinctrl-names = "default";
> > +	pinctrl-0 = <&gpio106_pins>;
> > +	rx-internal-delay-ps = <20>;
> > +	tx-internal-delay-ps = <100>;
> > +	status = "okay";
> > +
> > +	mdio {
> > +		compatible = "snps,dwmac-mdio";
> 
> Since it's implemented in the DWMAC IP, I think the mdio bus is
> SoC-specific and should be put into the SoC devicetree instead.
> 

Hi Yao Zi,

Thanks for the review.

You're right that the MDIO bus is implemented as part of the DWMAC IP and
is therefore SoC-specific. It makes more sense to describe the MDIO
controller in the SoC dtsi.

I'll move the MDIO node to eic7700.dtsi and keep only the PHY node in the
board dts in the next revision.

Thanks,
Zhi Li