[PATCH v2 5/5] iommu/riscv: Allow RISC_VIOMMU to COMPILE_TEST

[Jason Gunthorpe]

On Fri, Jan 30, 2026 at 01:58:51PM -0600, Andrew Jones wrote:
> >  config RISCV_IOMMU
> >  	bool "RISC-V IOMMU Support"
> > -	depends on RISCV && 64BIT
> > -	default y
> > +	default RISCV
> > +	depends on (RISCV || COMPILE_TEST) && 64BIT
> > +	depends on GENERIC_MSI_IRQ
> 
> This new depends isn't called out in the commit message. Maybe it should
> even be its own patch with a fixes d5f88acdd6ff ("iommu/riscv: Add support
> for platform msi") tag, but, either way, thanks for the fix.

I think if riscv has a 32 bit configuration with iommu HW available
then you'd want a different fix to make it work.. Probably include one
of the high/low headers to get emulated writeq

This is just intended to make it work with COMPILE_TEST on eg ARM32.

> > @@ -436,7 +436,9 @@ static unsigned int riscv_iommu_queue_send(struct riscv_iommu_queue *queue,
> >  	 * 6. Make sure the doorbell write to the device has finished before updating
> >  	 *    the shadow tail index in normal memory. 'fence o, w'
> >  	 */
> > +#ifdef CONFIG_MMIOWB
> >  	mmiowb();
> > +#endif
> 
> Taking inspiration from powerpc we'd put the #ifdef CONFIG_MMIOWB in
> arch/riscv/include/asm/mmiowb.h

That won't help compile on x86 for example.

Thanks,
Jason