[PATCH v2 5/5] iommu/riscv: Allow RISC_VIOMMU to COMPILE_TEST

[Andrew Jones]

On Tue, Jan 06, 2026 at 11:06:49AM -0400, Jason Gunthorpe wrote:
> This driver used to use a lot of page table constants from the architecture
> code which prevented COMPILE_TEST on other architectures. Now that iommupt
> provides all of the constants internally there are only two small bumps
> preventing COMPILE_TEST.
> 
> - Use the generic functions for the riscv specific phys_to_pfn() and
>   pfn_to_phys()
> 
> - Use CONFIG_MMIOWB to block off the mmiowb() barrier
> 
> Signed-off-by: Jason Gunthorpe <jgg at nvidia.com>
> ---
>  drivers/iommu/riscv/Kconfig      | 5 +++--
>  drivers/iommu/riscv/iommu-bits.h | 4 +++-
>  drivers/iommu/riscv/iommu.c      | 4 +++-
>  3 files changed, 9 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/iommu/riscv/Kconfig b/drivers/iommu/riscv/Kconfig
> index a329ec634cf1c5..f681188d19a1bc 100644
> --- a/drivers/iommu/riscv/Kconfig
> +++ b/drivers/iommu/riscv/Kconfig
> @@ -3,8 +3,9 @@
>  
>  config RISCV_IOMMU
>  	bool "RISC-V IOMMU Support"
> -	depends on RISCV && 64BIT
> -	default y
> +	default RISCV
> +	depends on (RISCV || COMPILE_TEST) && 64BIT
> +	depends on GENERIC_MSI_IRQ

This new depends isn't called out in the commit message. Maybe it should
even be its own patch with a fixes d5f88acdd6ff ("iommu/riscv: Add support
for platform msi") tag, but, either way, thanks for the fix.

>  	select IOMMU_API
>  	select GENERIC_PT
>  	select IOMMU_PT
> diff --git a/drivers/iommu/riscv/iommu-bits.h b/drivers/iommu/riscv/iommu-bits.h
> index 98daf0e1a30690..29a0040b1c32ea 100644
> --- a/drivers/iommu/riscv/iommu-bits.h
> +++ b/drivers/iommu/riscv/iommu-bits.h
> @@ -17,6 +17,7 @@
>  #include <linux/types.h>
>  #include <linux/bitfield.h>
>  #include <linux/bits.h>
> +#include <asm/page.h>
>  
>  /*
>   * Chapter 5: Memory Mapped register interface
> @@ -718,7 +719,8 @@ static inline void riscv_iommu_cmd_inval_vma(struct riscv_iommu_command *cmd)
>  static inline void riscv_iommu_cmd_inval_set_addr(struct riscv_iommu_command *cmd,
>  						  u64 addr)
>  {
> -	cmd->dword1 = FIELD_PREP(RISCV_IOMMU_CMD_IOTINVAL_ADDR, phys_to_pfn(addr));
> +	cmd->dword1 =
> +		FIELD_PREP(RISCV_IOMMU_CMD_IOTINVAL_ADDR, PHYS_PFN(addr));
>  	cmd->dword0 |= RISCV_IOMMU_CMD_IOTINVAL_AV;
>  }
>  
> diff --git a/drivers/iommu/riscv/iommu.c b/drivers/iommu/riscv/iommu.c
> index 4e2e08114bbf15..7a63f1771295b1 100644
> --- a/drivers/iommu/riscv/iommu.c
> +++ b/drivers/iommu/riscv/iommu.c
> @@ -160,7 +160,7 @@ static int riscv_iommu_queue_alloc(struct riscv_iommu_device *iommu,
>  	if (FIELD_GET(RISCV_IOMMU_PPN_FIELD, qb)) {
>  		const size_t queue_size = entry_size << (logsz + 1);
>  
> -		queue->phys = pfn_to_phys(FIELD_GET(RISCV_IOMMU_PPN_FIELD, qb));
> +		queue->phys = PFN_PHYS(FIELD_GET(RISCV_IOMMU_PPN_FIELD, qb));
>  		queue->base = devm_ioremap(iommu->dev, queue->phys, queue_size);
>  	} else {
>  		do {
> @@ -436,7 +436,9 @@ static unsigned int riscv_iommu_queue_send(struct riscv_iommu_queue *queue,
>  	 * 6. Make sure the doorbell write to the device has finished before updating
>  	 *    the shadow tail index in normal memory. 'fence o, w'
>  	 */
> +#ifdef CONFIG_MMIOWB
>  	mmiowb();
> +#endif

Taking inspiration from powerpc we'd put the #ifdef CONFIG_MMIOWB in
arch/riscv/include/asm/mmiowb.h

Thanks,
drew