[PATCH v3 5/5] riscv: dts: thead: Add reset controllers of more subsystems for TH1520

[Drew Fustini]

On Tue, Oct 14, 2025 at 01:10:32PM +0000, Yao Zi wrote:
> Describe reset controllers for VI, MISC, AP, DSP and AO subsystems. The
> one for AO subsystem is marked as reserved, since it may be used by AON
> firmware.
> 
> Signed-off-by: Yao Zi <ziyao at disroot.org>
> ---
>  arch/riscv/boot/dts/thead/th1520.dtsi | 37 +++++++++++++++++++++++++++
>  1 file changed, 37 insertions(+)
> 
> diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi
> index e680d1a7c821..15d64eaea89f 100644
> --- a/arch/riscv/boot/dts/thead/th1520.dtsi
> +++ b/arch/riscv/boot/dts/thead/th1520.dtsi
> @@ -277,6 +277,12 @@ clint: timer at ffdc000000 {
>  					      <&cpu3_intc 3>, <&cpu3_intc 7>;
>  		};
>  
> +		rst_vi: reset-controller at ffe4040100 {
> +			compatible = "thead,th1520-reset-vi";
> +			reg = <0xff 0xe4040100 0x0 0x8>;

Is this intentional so that the first VI_SUBSYS register, VISYS_SW_RST
at offset 0x100, will have an offset of 0 from the thead,th1520-reset-vi
reg in the driver?

[snip]
> +		rst_dsp: reset-controller at ffef040028 {
> +			compatible = "thead,th1520-reset-dsp";
> +			reg = <0xff 0xef040028 0x0 0x4>;

Similar to rst_vi, is this intentional so that the first register,
DSPSYS_SW_RST at offset 0x28, will have an offset of 0 in the driver?

Thanks,
Drew