[PATCH v2] riscv: asm: use .insn for making custom instructioons
Ben Dooks
ben.dooks at codethink.co.uk
Fri Oct 24 02:52:47 PDT 2025
On 24/10/2025 04:12, Paul Walmsley wrote:
> Hi Ben,
>
> On Thu, 23 Oct 2025, Ben Dooks wrote:
>
>> The assembler has .insn for building custom instructions
>> now, so remove the .4byte which also ensures the output
>> is marked as an instruction and not as data (which may
>> confuse both debuggers and anything else that relies on
>> this sort of marking)
>>
>> Add an ASM_INSN_I() wrapper in asm.h to allow the selecting
>> of how this is output so older assemblers are still good.
>>
>> Reviewed-by: Andrew Jones <ajones at ventanamicro.com>
>> Signed-off-by: Ben Dooks <ben.dooks at codethink.co.uk>
>> ---
>> v2:
>> - fixed #ifndef v #ifdef
>> - added custom MIPS instructions too
>> -
>> ---
>> arch/riscv/include/asm/asm.h | 6 ++++++
>> arch/riscv/include/asm/insn-def.h | 8 ++++----
>> arch/riscv/include/asm/vendor_extensions/mips.h | 6 +++---
>> 3 files changed, 13 insertions(+), 7 deletions(-)
>>
>
> [ ... ]
>
>> diff --git a/arch/riscv/include/asm/insn-def.h b/arch/riscv/include/asm/insn-def.h
>> index c9cfcea52cbb..a7860e6b908d 100644
>> --- a/arch/riscv/include/asm/insn-def.h
>> +++ b/arch/riscv/include/asm/insn-def.h
>> @@ -256,10 +256,10 @@
>> INSN_S(OPCODE_OP_IMM, FUNC3(6), __RS2(3), \
>> SIMM12((offset) & 0xfe0), RS1(base))
>>
>> -#define RISCV_PAUSE ".4byte 0x100000f"
>> -#define ZAWRS_WRS_NTO ".4byte 0x00d00073"
>> -#define ZAWRS_WRS_STO ".4byte 0x01d00073"
>> -#define RISCV_NOP4 ".4byte 0x00000013"
>> +#define RISCV_PAUSE ASM_INSN_I("0x100000f")
>> +#define ZAWRS_WRS_NTO ASM_INSN_I("0x00d00073")
>> +#define ZAWRS_WRS_STO ASM_INSN_I("0x01d00073")
>> +#define RISCV_NOP4 ASM_INSN(_U"0x00000013")
>
> This looks garbled. Is this intentional?
No, must have done this between writing it and saving.
Worse is it builds fine :/
Will do v3, thanks.
--
Ben Dooks http://www.codethink.co.uk/
Senior Engineer Codethink - Providing Genius
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