[PATCH] riscv: traps_misaligned: properly sign extend value in misaligned load handler

[Alexandre Ghiti]

Hi Andreas,

On 7/10/25 15:32, Andreas Schwab wrote:
> Add missing cast to signed long.
>
> Signed-off-by: Andreas Schwab <schwab at suse.de>
> ---
>   arch/riscv/kernel/traps_misaligned.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps_misaligned.c
> index 93043924fe6c..f760e4fcc052 100644
> --- a/arch/riscv/kernel/traps_misaligned.c
> +++ b/arch/riscv/kernel/traps_misaligned.c
> @@ -461,7 +461,7 @@ static int handle_scalar_misaligned_load(struct pt_regs *regs)
>   	}
>   
>   	if (!fp)
> -		SET_RD(insn, regs, val.data_ulong << shift >> shift);
> +		SET_RD(insn, regs, (long)(val.data_ulong << shift) >> shift);
>   	else if (len == 8)
>   		set_f64_rd(insn, regs, val.data_u64);
>   	else


Let's add:

Fixes: 956d705dd279 ("riscv: Unaligned load/store handling for M_MODE")

Cc: stable at vger.kernel.org

Does that fix the issue you reported when booting with opensbi 1.7?

Thanks,

Alex