[PATCH] riscv: traps_misaligned: properly sign extend value in misaligned load handler

[Clément Léger]

On 10/07/2025 15:32, Andreas Schwab wrote:
> Add missing cast to signed long.
> 
> Signed-off-by: Andreas Schwab <schwab at suse.de>
> ---
>  arch/riscv/kernel/traps_misaligned.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps_misaligned.c
> index 93043924fe6c..f760e4fcc052 100644
> --- a/arch/riscv/kernel/traps_misaligned.c
> +++ b/arch/riscv/kernel/traps_misaligned.c
> @@ -461,7 +461,7 @@ static int handle_scalar_misaligned_load(struct pt_regs *regs)
>  	}
>  
>  	if (!fp)
> -		SET_RD(insn, regs, val.data_ulong << shift >> shift);
> +		SET_RD(insn, regs, (long)(val.data_ulong << shift) >> shift);
>  	else if (len == 8)
>  		set_f64_rd(insn, regs, val.data_u64);
>  	else


Hi Andreas,

After modify my test to catch sign extension problems, I can confirm it
fixes it.

Tested-by: Clément Léger <cleger at rivosinc.com>

Thanks,

Clément