[PATCH v4] selftests: riscv: add misaligned access testing

Andreas Schwab schwab at suse.de
Thu Jul 10 06:53:32 PDT 2025


On Jul 10 2025, Clément Léger wrote:

> This selftest tests all the currently emulated instructions (except for
> the RV32 compressed ones which are left as a future exercise for a RV32
> user). For the FPU instructions, all the FPU registers are tested.

If that didn't catch the missing sign extension that I just fixed in
<https://lore.kernel.org/linux-riscv/mvmikk0goil.fsf@suse.de>, you
should consider extending the tests.

-- 
Andreas Schwab, SUSE Labs, schwab at suse.de
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