[PATCH] riscv: dts: starfive: add pcie1 on the star64

[Conor Dooley]

From: Conor Dooley <conor.dooley at microchip.com>

It was reported to me that the star64 actually /does/ have an exposed
PCIe port, despite the commit message there. In my original conversation
with Minda, they said that pcie1 was available there and pcie0 was not,
but the v2 patch didn't actually add pcie1 on the star64.

Signed-off-by: Conor Dooley <conor.dooley at microchip.com>
---
I think I'll just squash this in and fixup the commit message, since the
patch is still at the top of my branch.

CC: Minda Chen <minda.chen at starfivetech.com>
CC: Conor Dooley <conor at kernel.org>
CC: Rob Herring <robh+dt at kernel.org>,
CC: Emil Renner Berthing <emil.renner.berthing at canonical.com
CC: Krzysztof Kozlowski <krzysztof.kozlowski+dt at linaro.org
CC: devicetree at vger.kernel.org
CC: linux-kernel at vger.kernel.org
CC: linux-riscv at lists.infradead.org
---
 arch/riscv/boot/dts/starfive/jh7110-pine64-star64.dts | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/riscv/boot/dts/starfive/jh7110-pine64-star64.dts b/arch/riscv/boot/dts/starfive/jh7110-pine64-star64.dts
index 2d41f18e0359..b720cdd15ed6 100644
--- a/arch/riscv/boot/dts/starfive/jh7110-pine64-star64.dts
+++ b/arch/riscv/boot/dts/starfive/jh7110-pine64-star64.dts
@@ -39,6 +39,10 @@ phy1: ethernet-phy at 1 {
 	};
 };
 
+&pcie1 {
+	status = "okay";
+};
+
 &phy0 {
 	rx-internal-delay-ps = <1900>;
 	tx-internal-delay-ps = <1500>;
-- 
2.43.0