[PATCH 4/5] clk: sophgo: Add SG2042 clock generator driver

[kernel test robot]

Hi Chen,

kernel test robot noticed the following build warnings:

[auto build test WARNING on b85ea95d086471afb4ad062012a4d73cd328fa86]

url:    https://github.com/intel-lab-lkp/linux/commits/Chen-Wang/dt-bindings-clock-sophgo-Add-SG2042-clock-definitions/20231113-212401
base:   b85ea95d086471afb4ad062012a4d73cd328fa86
patch link:    https://lore.kernel.org/r/1000e8d546514973364478271564356352a46ed5.1699879741.git.unicorn_wang%40outlook.com
patch subject: [PATCH 4/5] clk: sophgo: Add SG2042 clock generator driver
config: riscv-rv32_defconfig (https://download.01.org/0day-ci/archive/20231119/202311191920.5xIUxW5n-lkp@intel.com/config)
compiler: clang version 17.0.0 (https://github.com/llvm/llvm-project.git 4a5ac14ee968ff0ad5d2cc1ffa0299048db4c88a)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20231119/202311191920.5xIUxW5n-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp at intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202311191920.5xIUxW5n-lkp@intel.com/

All warnings (new ones prefixed by >>):

>> drivers/clk/sophgo/clk-sophgo-sg2042.c:217:44: warning: overflow in expression; result is -1094967296 with type 'long' [-Winteger-overflow]
     217 |                         if (foutvco < PLL_FREQ_MIN || foutvco > PLL_FREQ_MAX
         |                                                                 ^
   drivers/clk/sophgo/clk-sophgo-sg2042.c:25:28: note: expanded from macro 'PLL_FREQ_MAX'
      25 | #define PLL_FREQ_MAX (3200 * MHZ)
         |                            ^
   1 warning generated.


vim +/long +217 drivers/clk/sophgo/clk-sophgo-sg2042.c

   201	
   202	static int __sg2042_get_pll_ctl_setting(
   203		struct sg2042_pll_ctrl *best,
   204		unsigned long req_rate,
   205		unsigned long parent_rate)
   206	{
   207		int ret;
   208		unsigned int fbdiv, refdiv, fref, postdiv1, postdiv2;
   209		unsigned long tmp = 0, foutvco;
   210	
   211		fref = parent_rate;
   212	
   213		for (refdiv = REFDIV_MIN; refdiv < REFDIV_MAX + 1; refdiv++) {
   214			for (fbdiv = FBDIV_MIN; fbdiv < FBDIV_MAX + 1; fbdiv++) {
   215				foutvco = fref * fbdiv / refdiv;
   216				/* check fpostdiv pfd */
 > 217				if (foutvco < PLL_FREQ_MIN || foutvco > PLL_FREQ_MAX
   218						|| (fref / refdiv) < 10)
   219					continue;
   220	
   221				ret = __sg2042_pll_get_postdiv_1_2(req_rate, fref, fbdiv,
   222						refdiv, &postdiv1, &postdiv2);
   223				if (ret)
   224					continue;
   225	
   226				tmp = foutvco / (postdiv1 * postdiv2);
   227				if (abs_diff(tmp, req_rate) < abs_diff(best->freq, req_rate)) {
   228					best->freq = tmp;
   229					best->refdiv = refdiv;
   230					best->fbdiv = fbdiv;
   231					best->postdiv1 = postdiv1;
   232					best->postdiv2 = postdiv2;
   233					if (tmp == req_rate)
   234						return 0;
   235				}
   236				continue;
   237			}
   238		}
   239	
   240		return 0;
   241	}
   242	

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