[PATCH 5/5] riscv: dts: add clock generator for Sophgo SG2042 SoC

[Chen Wang]

From: Chen Wang <unicorn_wang at outlook.com>

Add clock generator node to device tree for SG2042, and enable clock for
uart0.

Signed-off-by: Chen Wang <unicorn_wang at outlook.com>
---
 arch/riscv/boot/dts/sophgo/sg2042-clock.dtsi | 76 ++++++++++++++++++++
 arch/riscv/boot/dts/sophgo/sg2042.dtsi       | 10 +++
 2 files changed, 86 insertions(+)
 create mode 100644 arch/riscv/boot/dts/sophgo/sg2042-clock.dtsi

diff --git a/arch/riscv/boot/dts/sophgo/sg2042-clock.dtsi b/arch/riscv/boot/dts/sophgo/sg2042-clock.dtsi
new file mode 100644
index 000000000000..66d2723fab35
--- /dev/null
+++ b/arch/riscv/boot/dts/sophgo/sg2042-clock.dtsi
@@ -0,0 +1,76 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2023 Sophgo Technology Inc. All rights reserved.
+ */
+
+/ {
+	cgi: oscillator {
+		compatible = "fixed-clock";
+		clock-frequency = <25000000>;
+		clock-output-names = "cgi";
+		#clock-cells = <0>;
+	};
+
+	clkgen: clock-controller {
+		compatible = "sophgo,sg2042-clkgen";
+		#clock-cells = <1>;
+		system-ctrl = <&sys_ctrl>;
+		clocks = <&cgi>;
+		assigned-clocks = \
+			<&clkgen DIV_CLK_FPLL_RP_CPU_NORMAL_1>,
+			<&clkgen DIV_CLK_FPLL_50M_A53>,
+			<&clkgen DIV_CLK_FPLL_TOP_RP_CMN_DIV2>,
+			<&clkgen DIV_CLK_FPLL_UART_500M>,
+			<&clkgen DIV_CLK_FPLL_AHB_LPC>,
+			<&clkgen DIV_CLK_FPLL_EFUSE>,
+			<&clkgen DIV_CLK_FPLL_TX_ETH0>,
+			<&clkgen DIV_CLK_FPLL_PTP_REF_I_ETH0>,
+			<&clkgen DIV_CLK_FPLL_REF_ETH0>,
+			<&clkgen DIV_CLK_FPLL_EMMC>,
+			<&clkgen DIV_CLK_FPLL_SD>,
+			<&clkgen DIV_CLK_FPLL_TOP_AXI0>,
+			<&clkgen DIV_CLK_FPLL_TOP_AXI_HSPERI>,
+			<&clkgen DIV_CLK_FPLL_AXI_DDR_1>,
+			<&clkgen DIV_CLK_FPLL_DIV_TIMER1>,
+			<&clkgen DIV_CLK_FPLL_DIV_TIMER2>,
+			<&clkgen DIV_CLK_FPLL_DIV_TIMER3>,
+			<&clkgen DIV_CLK_FPLL_DIV_TIMER4>,
+			<&clkgen DIV_CLK_FPLL_DIV_TIMER5>,
+			<&clkgen DIV_CLK_FPLL_DIV_TIMER6>,
+			<&clkgen DIV_CLK_FPLL_DIV_TIMER7>,
+			<&clkgen DIV_CLK_FPLL_DIV_TIMER8>,
+			<&clkgen DIV_CLK_FPLL_100K_EMMC>,
+			<&clkgen DIV_CLK_FPLL_100K_SD>,
+			<&clkgen DIV_CLK_FPLL_GPIO_DB>,
+			<&clkgen DIV_CLK_MPLL_RP_CPU_NORMAL_0>,
+			<&clkgen DIV_CLK_MPLL_AXI_DDR_0>;
+		assigned-clock-rates = \
+			<2000000000>,
+			<50000000>,
+			<1000000000>,
+			<500000000>,
+			<200000000>,
+			<25000000>,
+			<125000000>,
+			<50000000>,
+			<25000000>,
+			<100000000>,
+			<100000000>,
+			<100000000>,
+			<250000000>,
+			<1000000000>,
+			<50000000>,
+			<50000000>,
+			<50000000>,
+			<50000000>,
+			<50000000>,
+			<50000000>,
+			<50000000>,
+			<50000000>,
+			<100000>,
+			<100000>,
+			<100000>,
+			<2000000000>,
+			<1000000000>;
+	};
+};
diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
index 93256540d078..de79c0cdb4c1 100644
--- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi
+++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
@@ -5,8 +5,10 @@
 
 /dts-v1/;
 #include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/clock/sophgo-sg2042-clk.h>
 
 #include "sg2042-cpus.dtsi"
+#include "sg2042-clock.dtsi"
 
 / {
 	compatible = "sophgo,sg2042";
@@ -311,12 +313,20 @@ intc: interrupt-controller at 7090000000 {
 			riscv,ndev = <224>;
 		};
 
+		sys_ctrl: syscon at 7030010000 {
+			compatible = "sophgo,sg2042-syscon", "syscon";
+			reg = <0x70 0x30010000 0x0 0x8000>;
+		};
+
 		uart0: serial at 7040000000 {
 			compatible = "snps,dw-apb-uart";
 			reg = <0x00000070 0x40000000 0x00000000 0x00001000>;
 			interrupt-parent = <&intc>;
 			interrupts = <112 IRQ_TYPE_LEVEL_HIGH>;
 			clock-frequency = <500000000>;
+			clocks = <&clkgen GATE_CLK_UART_500M>,
+				 <&clkgen GATE_CLK_APB_UART>;
+			clock-names = "baudclk", "apb_pclk";
 			reg-shift = <2>;
 			reg-io-width = <4>;
 			status = "disabled";
-- 
2.25.1