[PATCH 2/2] RISC-V: fix the comment for ISA string workaround

[Tsukasa OI]

On 2023/07/22 19:52, Conor Dooley wrote:
> On Sat, Jul 22, 2023 at 06:22:38AM +0000, Tsukasa OI wrote:
>> From: Tsukasa OI <research_trasio at irq.a4lg.com>
>>
>> Extensions prefixed with "Su" won't corrupt the workaround in many
>> cases.  The only exception is when the first multi-letter extension in the
>> ISA string begins with "Su" and is not prefixed with an underscore.
>>
>> For instance, following ISA string can confuse this QEMU workaround.
>>
>> *   "rv64imacsuclic" (RV64I + M + A + C + "Suclic")
>>
>> However, this case is very unlikely because extensions prefixed by either
>> "Z", "Sm" or "Ss" will most likely precede first.
>>
>> For instance, the "Suclic" extension (draft as of now) will be placed after
>> related "Smclic" and "Ssclic" extensions.  It's also highly likely that
>> other unprivileged extensions like "Zba" will precede.
>>
>> It's also possible to suppress the issue in the QEMU workaround with an
>> underscore.  Following ISA string won't confuse the QEMU workaround.
>>
>> *   "rv64imac_suclic" (RV64I + M + A + C + delimited "Suclic")
>>
>> This fix is to tell kernel developers the nature of this workaround
>> precisely.  There are some "Su*" extensions to be ratified but don't worry
>> about this workaround too much.
>>
> 
>> This commit comes with another minor editorial fix.
> 
> Which is what?
> 
> The new wording is fine by me though..
> Reviewed-by: Conor Dooley <conor.dooley at microchip.com>

1. Use of plurals ("letters" and "bits")
2. Second "'s' & 'u'" to "'s' and 'u'"
3. Spacing after the first "'s' & 'u'" (before "(QEMU).")

It feels they are too minor to separate to another commit.
At least I should replace the commit message to "other minor editorial
fixes" and... should I clarify editorial fixes?

Thanks,
Tsukasa

> 
> Thanks,
> Conor.
> 
>> Signed-off-by: Tsukasa OI <research_trasio at irq.a4lg.com>
>> ---
>>  arch/riscv/kernel/cpufeature.c | 9 +++++----
>>  1 file changed, 5 insertions(+), 4 deletions(-)
>>
>> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
>> index 63277cdc1ea5..91f1ef3e762c 100644
>> --- a/arch/riscv/kernel/cpufeature.c
>> +++ b/arch/riscv/kernel/cpufeature.c
>> @@ -170,10 +170,11 @@ void __init riscv_fill_hwcap(void)
>>  			case 's':
>>  			case 'S':
>>  				/*
>> -				 * Workaround for invalid single-letter 's' & 'u'(QEMU).
>> -				 * No need to set the bit in riscv_isa as 's' & 'u' are
>> -				 * not valid ISA extensions. It works until multi-letter
>> -				 * extension starting with "Su" appears.
>> +				 * Workaround for invalid single-letters 's' & 'u' (QEMU).
>> +				 * No need to set the bits in riscv_isa as 's' and 'u' are
>> +				 * not valid ISA extensions. It works unless the first multi-letter
>> +				 * extension in the ISA string begins with "Su" and not prefixed
>> +				 * with an underscore.
>>  				 */
>>  				if (ext[-1] != '_' && tolower(ext[1]) == 'u') {
>>  					++isa;
>> -- 
>> 2.40.0
>>
>>
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