[PATCH 1/2] RISC-V: make ISA string workaround case-insensitive

[Conor Dooley]

On Sat, Jul 22, 2023 at 06:22:37AM +0000, Tsukasa OI wrote:
> From: Tsukasa OI <research_trasio at irq.a4lg.com>
> 
> This is a follow-up for commit 255b34d799dd ("riscv: allow case-insensitive
> ISA string parsing").
> 
> Although the QEMU workaround in the ISA string parser works well with
> lowercase-only handling ('s' followed by 'u' and not preceded by '_'),
> case-sensitive handling in the case-insensitive parser can be confusing.

> This commit makes the QEMU workaround case-insensitive and gives more
> robustness (against manually crafted Device Tree blobs) and less confusion
> to kernel developers.

If people are manually crafting their DT, they should check it for
compliance with dt-validate (or dtbs_check). The case insensitivity only
makes sense for ACPI, but by the time ACPI was supported, you'd already
removed the "su" stuff from QEMU.

Thanks,
Conor.

> 
> Signed-off-by: Tsukasa OI <research_trasio at irq.a4lg.com>
> ---
>  arch/riscv/kernel/cpufeature.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index a8f66c015229..63277cdc1ea5 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -168,19 +168,19 @@ void __init riscv_fill_hwcap(void)
>  
>  			switch (*ext) {
>  			case 's':
> +			case 'S':
>  				/*
>  				 * Workaround for invalid single-letter 's' & 'u'(QEMU).
>  				 * No need to set the bit in riscv_isa as 's' & 'u' are
>  				 * not valid ISA extensions. It works until multi-letter
>  				 * extension starting with "Su" appears.
>  				 */
> -				if (ext[-1] != '_' && ext[1] == 'u') {
> +				if (ext[-1] != '_' && tolower(ext[1]) == 'u') {
>  					++isa;
>  					ext_err = true;
>  					break;
>  				}
>  				fallthrough;
> -			case 'S':
>  			case 'x':
>  			case 'X':
>  			case 'z':
> -- 
> 2.40.0
> 
> 
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