[PATCH 1/2] RISC-V: make ISA string workaround case-insensitive

[Tsukasa OI]

From: Tsukasa OI <research_trasio at irq.a4lg.com>

This is a follow-up for commit 255b34d799dd ("riscv: allow case-insensitive
ISA string parsing").

Although the QEMU workaround in the ISA string parser works well with
lowercase-only handling ('s' followed by 'u' and not preceded by '_'),
case-sensitive handling in the case-insensitive parser can be confusing.

This commit makes the QEMU workaround case-insensitive and gives more
robustness (against manually crafted Device Tree blobs) and less confusion
to kernel developers.

Signed-off-by: Tsukasa OI <research_trasio at irq.a4lg.com>
---
 arch/riscv/kernel/cpufeature.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index a8f66c015229..63277cdc1ea5 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -168,19 +168,19 @@ void __init riscv_fill_hwcap(void)
 
 			switch (*ext) {
 			case 's':
+			case 'S':
 				/*
 				 * Workaround for invalid single-letter 's' & 'u'(QEMU).
 				 * No need to set the bit in riscv_isa as 's' & 'u' are
 				 * not valid ISA extensions. It works until multi-letter
 				 * extension starting with "Su" appears.
 				 */
-				if (ext[-1] != '_' && ext[1] == 'u') {
+				if (ext[-1] != '_' && tolower(ext[1]) == 'u') {
 					++isa;
 					ext_err = true;
 					break;
 				}
 				fallthrough;
-			case 'S':
 			case 'x':
 			case 'X':
 			case 'z':
-- 
2.40.0